ADPA7005CHIP datasheet(19/23 Pages) AD

19 / 23 page

Data Sheet

ADPA7005CHIP

Rev. 0 | Page 19 of 23

HMC980LP4E BIAS SEQUENCE

The dc supply sequencing in the Power-Up Sequence section

and the Power-Down Sequence section is required to prevent

damage to the HMC980LP4E when using it to control the

ADPA7005CHIP.

Power-Up Sequence

The power-up sequence is as follows:

VDIG = 3.3 V

S0 = 3.3 V

VDD = 5.68 V

VNEG = −1.5 V (unnecessary if using internally

generated voltage)

EN = 3.3 V (transition from 0 V to 3.3 V turns on VGATE

and VDRAIN)

Power-Down Sequence

The power-down sequence is as follows:

EN = 0 V (transition from 3.3 V to 0 V turns off VDRAIN

and VGATE)

VNEG = 0 V (unnecessary if using internally generated

voltage)

VDD = 0 V

S0 = 0 V

VDIG = 0 V

After the HMC980LP4E bias control circuit is set up, toggle

the bias to the ADPA7005CHIP on or off by applying 3.3 V or

0 V, respectively, to the EN pad. At EN = 3.3 V, VGATE drops to

−1.5 V and VDRAIN turns on at 5 V. VGATE then rises until

IDRAIN = 800 mA, and the closed control loop regulates IDRAIN at

1600 mA. When EN = 0 V, VGATE is set to −1.5 V, and

VDRAIN is set to 0 V (see Figure 57 and Figure 58).

Figure 57. Turn On HMC980LP4E Outputs to ADPA7005CHIP

Figure 58. Turn Off HMC980LP4E Outputs to ADPA7005CHIP

CONSTANT DRAIN CURRENT BIASING vs.

CONSTANT GATE VOLTAGE BIASING

The HMC980LP4E uses a closed-loop feedback to continuously

adjust VGATE to maintain a constant gate current bias over dc

supply variation, temperature, and part to part variation. In

addition, constant drain current bias is the optimum method

for reducing time in calibration procedures and for maintaining

consistent performance over time. By comparing with a constant

gate voltage bias where the current is driven to increase when RF

power is applied, a slightly lower output P1dB is seen with a

constant drain current bias. This output P1db is displayed in

Figure 62, where the RF performance is slightly lower than

constant gate voltage bias operation due to a lower drain current at

the high input powers as the device reaches 1 dB compression.

The output P1dB performance for constant drain current bias

can be increased towards constant gate voltage bias

performance by increasing the set current towards the IDD it

would reach under RF drive in the constant gate voltage bias

condition, as shown in Figure 62. The limit of increasing IDQ

under the constant current operation is set by the thermal

limitations that can be found in the absolute maximum ratings

table (see Table 3) from the amplifier data sheet with the

maximum power dissipation specification. As the IDD increase

continues, the actual output P1dB does not continue to increase

indefinitely, and the power dissipation increases. Therefore,

take the exchange between the power dissipation and output

P1dB performance into consideration when using constant

drain current biasing.

CH1 2V

CH3 2V

CH2 1V

CH4 2V

M20.0ms

A CH1

1.12V

50.00%

VDD

VDRAIN

VGATE

CH1 2V

CH3 2V

CH2 1V

CH4 2V

M20.0ms

A CH1

1.12V

50.00%

VDD

VDRAIN

VGATE

ADPA7005CHIP Scheda tecnica(PDF) 19 Page - Analog Devices

ADPA7005CHIP Scheda tecnica(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Scheda tecnica Scarica

Link URL