P5021 datasheet(151/155 Pages) NXP

151 / 155 page

Package information

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

151

This figure depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board.

Figure 63. Package with heat sink mounted to a printed-circuit board

The heat sink removes most of the heat from the device. Heat generated on the active side of the chip is conducted through the

silicon and through the heat sink attach material (or thermal interface material), and finally to the heat sink. The junction-to-case

thermal resistance is low enough that the heat sink attach material and heat sink thermal resistance are the dominant terms.

3.8.2

Thermal interface materials

A thermal interface material is required at the package-to-heat sink interface to minimize the thermal contact resistance. The

performance of thermal interface materials improves with increasing contact pressure; this performance characteristic chart is

generally provided by the thermal interface vendor. The recommended method of mounting heat sinks on the package is by

means of a spring clip attachment to the printed-circuit board (see Figure 62).

The system board designer can choose among several types of commercially-available thermal interface materials.

Package information

The following section describes the detailed content and mechanical description of the package.

4.1

Package parameters for the FC-PBGA

The package parameters are as provided in the following list. The package type is 37.5 mm

× 37.5 mm, 1295 flip-chip,

plastic-ball, grid array (FC-PBGA).

Package outline

37.5 mm

× 37.5 mm

Interconnects

1295

Ball Pitch

1.0 mm

Ball Diameter (typical)

0.60 mm

Solder Balls

96.5% Sn, 3% Ag, 0.5% Cu

Module height (typical)

2.88 mm to 3.53 mm (Maximum)

External resistance

Internal resistance

Radiation

Convection

Radiation

Convection

Heat sink

Printed-circuit board

Thermal interface material

Package/solder balls

Die junction

Die/Package

(Note the internal versus external package resistance)

Junction to lid top

Junction to case top

P5021 Scheda tecnica(PDF) 151 Page - NXP Semiconductors

P5021 Scheda tecnica(HTML) 151 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL