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P5021 Scheda tecnica(PDF) 147 Page - NXP Semiconductors |
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P5021 Scheda tecnica(HTML) 147 Page - NXP Semiconductors |
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147 / 155 page ![]() Hardware design considerations P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 147 Figure 60. Aurora 70 pin connector duplex interface connection PORESET From Target Board Sources RESET 22 HRESET VIO VSense2 2 1 k Ω COP_TMS COP_TDO COP_TDI COP_TCK TMS TDO TDI 6 10 8 12 TRST 4 42,47,48,53,54, 29,30,35,36,41, (if any) Notes: TRST1 10 k Ω 10 k Ω 10 k Ω Duplex 70 HRESET 2. Populate this with a 1 k Ω resistor for short-circuit/current-limiting protection. OVDD 10 k Ω PORESET1 in order to fully control the processor as shown here. 1. The Aurora port and target board should be able to independently assert PORESET and TRST to the processor TCK 3 3.This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to position B. 10 k Ω 4 4. Asserting HRESET causes a hard reset on the device. to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed A B 20 Vendor I/O 3 N/C 18 Vendor I/O 2 (Aurora Event Out) 16 Vendor I/O 1 (Aurora Event In) 14 Vendor I/O 0 (Aurora HALT) 5,11,17,23,24, EVT[4] EVT[1] EVT[0] 1 TX0_P 3 TX0_N SD_TX09_P SD_TX09_N 7 TX1_P 9 TX1_N SD_TX08_P SD_TX08_N 13 RX0_P 15 RX0_N SD_RX09_P SD_RX09_N 19 RX1_P 21 RX1_N SD_RX08_P SD_RX08_N 3 13 9 5 1 6 10 15 11 7 16 12 8 4 1 2 17 18 20 19 21 22 14 25 35 31 27 23 28 32 37 33 29 38 34 30 26 24 39 40 42 41 43 44 36 47 57 53 49 50 54 59 55 51 60 56 52 48 45 46 61 62 64 63 65 66 58 68 67 69 70 34 Vendor I/O 5 (Aurora HRESET) 32 Vendor I/O 4 N/C EVT[4] 31,33,37,38, N/C 39,40,43,44, 45,46,49,50, 51,52,55,56, 57,58,61,62, 63,64,67,68, 25,26,27,28, 69,70 59,60,65,66 Connector Physical Pinout 10 k Ω 10 k Ω Chip |
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