P5021 datasheet(143/155 Pages) NXP

143 / 155 page

Hardware design considerations

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

143

Figure 56. Legacy JTAG interface connection

PORESET

From Target

Board Sources

COP_HRESET

COP_SRESET

HRESET

COP_VDD_SENSE2

10 k

COP_CHKSTP_IN

COP_TMS

COP_TDO

COP_TDI

COP_TCK

TMS

TDO

TDI

COP_TRST

(if any)

14 3

Notes:

10 k

TRST1

10 k

CKSTP_OUT

COP_CHKSTP_OUT

KEY

No pin

COP Connector

Physical Pinout

HRESET

2. Populate this with a 10

Ω resistor for short-circuit/current-limiting protection.

OVDD

10 k

PORESET1

in order to fully control the processor as shown here.

1. The COP port and target board should be able to independently assert PORESET and TRST to the processor

signal integrity.

TCK

5.This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing

to position B.

10 k

6. Asserting HRESET causes a hard reset on the device.

3. The KEY location (pin 14) is not physically present on the COP header.

4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for improved

to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed

System logic

Chip

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