FEDL7732-01-10

OKI Semiconductor

MSM7732-01

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SG

Analog signal ground.

The output voltage of this pin is approximately 1.4 V. Put the bypass capacitors (10 µF in parallel with 0.1 µF

ceramic type) between this pin and AG to get the specified noise characteristics. During power-down, this output

voltage is 0 V.

AMPAI, AMPAO

Used for amplifier A. The pin AMPAI is connected to the amplifier A inverting input, and the pin AMPAO is

connected to the amplifier A output.

SWA, SWB, SWC

Used for the internal analog switch. The pin SWB connects to the pin SWA or the pin SWC. This is controlled by

CR1-B1.

SWD, SWE

Used for the internal analog switch. The pin SWD connects to the pin SWE or not. This is controlled by CR1-B2.

Since these pins are separated in the device, connect them as close as possible on the PCB.

DG, AG1, AG2

Ground. DG is the digital system ground. AG1 and AG2 are connected to the analog system ground.

The DG pin must be kept as close as possible to AG1 and AG2 on the PCB.

PDN

Power down and reset control input.

When set to digital “0”, the system changes to the power down state and control registers are reset. Since the power

down mode is controlled by a logical OR with CR0-B5 of the control register, set CR0-B5 to logic “0” when using

this pin.

Be sure to reset the control registers by executing this power down to keep this pin to digital “0” level for 200 ns or

MCK

Master clock input.

The frequency must be 2.048 MHz. MCK can be asynchronous with SYNC and BCLK.

BCLK

Shift clock input for the PCM data.

The frequency is set in the range of 64 kHz to 2048 kHz.