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MSM7732-01TB Scheda tecnica(PDF) 15 Page - OKI electronic componets |
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MSM7732-01TB Scheda tecnica(HTML) 15 Page - OKI electronic componets |
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15 / 29 page ![]() FEDL7732-01-10 OKI Semiconductor MSM7732-01 15/29 TIMING DIAGRAM Transmit Side PCM Timing (Normal Synchronous Interface) When tSB >= 0, the Delay of the MSB is defined as tXD1. When tSB < 0, the Delay of the MSB is defined as t SDX. Transmit Side PCM Timing (Short Frame Synchronous Interface) Receive Side PCM Timing (Normal Synchronous Interface) Receive Side PCM Timing (Short Frame Synchronous Interface) Figure 4 PCM Interface Timing MSB LSB tXD3 0 tWS tXD1 tXD2 BCLK SYNC PCMOUT 1 2 3 4 5 6 7 8 9 10 tSB tBS MSB LSB tRD3 0 tWS tRD1 tRD2 BCLK SYNC PCMIN 1 2 3 4 5 6 7 8 9 10 tSB tBS MSB LSB tRD3 0 tSDR tWS tSB tRD1 tRD2 BCLK SYNC PCMIN 1 2 3 4 5 6 7 8 9 10 MSB LSB tXD3 0 tSDX tWS tSB tXD1 tXD2 BCLK SYNC PCMOUT 1 2 3 4 5 6 7 8 9 10 |
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