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ADP1972

Data Sheet

APPLICATIONS INFORMATION

The ADP1972 has many programmable features that are

optimized and controlled for a given application. The ADP1972

provides pins for selecting the operating mode, controlling the

current limit, selecting an internal or external clock, setting the

operating frequency, phase shifting the operating frequency,

programming the maximum duty cycle, and adjusting the

soft start.

BUCK OR BOOST SELECTION

To operate the ADP1972 in boost/recycle mode, apply a voltage

less than 1.05 V (typical) to the MODE pin. To operate the

ADP1972 in buck/discharge mode, drive the MODE pin high,

greater than 1.2 V (typical). The state of the MODE pin can

only be changed when the ADP1972 is shutdown via the EN

pin, or disabled via an external fault condition signaled on the

FAULT pin, a TSD event, or a UVLO condition.

SELECTING RS TO SET THE CURRENT LIMIT

See Figure 21 for the current-limit block diagram for peak

current-limit control. Use using the following equation to set

the current limit:

(

)

100

mA =

(1)

where:

IPK is the desired peak current-limit in mA.

RS is the sense resistor used to set the peak current limit in Ω.

When the ADP1972 is configured to operate in buck/charge

mode, the internal current-limit reference is set to 300 mV

(typical). When the ADP1972 is configured to operate in

boost/recycle mode, the internal current-limit reference is set to

500 mV (typical). The external resistor, RCL, is needed to offset

the current properly to detect the peak in both buck and boost

operation. Set the value of RCL to 20 kΩ. In operation, the

equation for setting the peak current follows:

For buck/charge mode, it is

VREF (BUCK) = (ICL) × (RCL) − (IPK) × (RS)

(2)

For boost/recycle mode, it is

VREF (BOOST) = (ICL) × (RCL) + (IPK) × (RS)

(3)

where:

VREF (BUCK) = 300 mV, typical.

VREF (BOOST) = 500 mV, typical.

ICL = 20 µA, typical.

RCL = 20 kΩ.

The ADP1972 is designed so that the peak current limit is

the same in both the buck mode and boost mode of operation.

A 1% or better tolerance for the RCL and RS resistors is

recommended.

ADJUSTING THE OPERATING FREQUENCY

If the SCFG pin is tied to VREG, forcing VSCFG ≥ 4.53 V, or if

SCFG is left floating and internally tied to VREG, the ADP1972

operates at the frequency set by RFREQ, and the SYNC pin outputs

a clock at the programmed frequency. When VSCFG ≥ 4.53 V, the

output clock on the SYNC pin can be used as a master clock in

applications that require synchronization.

If VSCFG is ≤ 0.5 V, the SYNC pin is configured as an input,

and the ADP1972 operates as a slave device. As a slave device,

the ADP1972 synchronizes to the external clock applied to

the SYNC pin. If the voltage applied to the SCFG pin is

0.65 V < VSCFG < 4.25 V, and a resistor is connected between

SCFG and ground, the SYNC pin is configured as an input,

and the ADP1972 synchronizes to a phase shifted version of the

external clock applied to the SYNC pin.

Whether operating the ADP1972 as a master or as a slave

device, RFREQ must be carefully selected using the equations in

the following sections.

Selecting RFREQ for a Master Device

When VSCFG is ≥ 4.53 V, the ADP1972 operates as a master device.

When functioning as a master device, the ADP1972 operates at

the frequency set by the external RFREQ resistor connected between

FREQ and ground, and the ADP1972 outputs a clock at the

programmed frequency on the SYNC pin.

Figure 22 shows the relationship between the programmed

switching frequency (fSET) and the value of RFREQ.

210

110

130

150

170

190

100

150

200

250

300

fSET (kHz)

Figure 22. RFREQ vs. Switching Frequency (fSET)

Use the following equation to calculate the RFREQ value for a

desired master clock synchronization frequency:

( )

(kHz)

kΩ

)

(

SET

MASTER

FREQ

(4)

where:

fSET is the switching frequency in kHz.

RFREQ (MASTER) is the resistor in kΩ to set the frequency for master

devices.

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