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STM32G070KB Scheda tecnica(PDF) 70 Page - STMicroelectronics |
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STM32G070KB Scheda tecnica(HTML) 70 Page - STMicroelectronics |
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70 / 93 page ![]() Electrical characteristics STM32G070CB/KB/RB 70/93 DS12766 Rev 2 6 bits 1.5 43 390 3.5 100 2200 7.5 214 5600 12.5 357 10000 19.5 557 15000 39.5 1129 33000 79.5 2271 50000 160.5 4586 50000 1. Guaranteed by design. 2. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and disabled when VDDA ≥ 2.4 V. Table 53. Maximum ADC RAIN . (continued) Resolution Sampling cycle at 35 MHz Sampling time at 35 MHz [ns] Max. RAIN(1)(2) (Ω) Table 54. ADC accuracy(1)(2)(3) Symbol Parameter Conditions(4) Min Typ Max Unit ET Total unadjusted error VDDA=VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range -3 6.5 LSB EO Offset error VDDA=VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range -1.5 4.5 LSB EG Gain error VDDA=VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range -3 5 LSB ED Differential linearity error VDDA=VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range -1.2 1.5 LSB EL Integral linearity error VDDA=VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range -2.5 3 LSB ENOB Effective number of bits VDDA=VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range 9.6 10.2 - bit SINAD Signal-to-noise and distortion ratio VDDA=VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range 59.5 63 - dB SNR Signal-to-noise ratio VDDA=VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range 60 64 - dB THD Total harmonic distortion VDDA=VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range --74 -70 dB |
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