MCIMX503CVM8B datasheet(90/136 Pages) NXP

90 / 136 page

i.MX50 Applications Processors for Consumer Products, Rev. 7

Electrical Characteristics

Freescale Semiconductor

4.9.9.1

SSI Transmitter Timing with Internal Clock

Figure 51 depicts the SSI transmitter internal clock timing and Table 66 lists the timing parameters for

the SSI transmitter internal clock.

Figure 51. SSI Transmitter Internal Clock Timing Diagram

Table 66. SSI Transmitter Timing with Internal Clock

Parameter

Min

Max

Unit

Internal Clock Operation

SS1

(Tx/Rx) CK clock period

81.4

—

SS2

(Tx/Rx) CK clock high period

36.0

—

SS3

(Tx/Rx) CK clock rise time

—

6.0

SS4

(Tx/Rx) CK clock low period

36.0

—

SS5

(Tx/Rx) CK clock fall time

—

6.0

SS6

(Tx) CK high to FS (bl) high

—

15.0

SS8

(Tx) CK high to FS (bl) low

—

15.0

SS10

(Tx) CK high to FS (wl) high

—

15.0

SS12

(Tx) CK high to FS (wl) low

—

15.0

SS14

(Tx/Rx) Internal FS rise time

—

6.0

SS15

(Tx/Rx) Internal FS fall time

—

6.0

SS16

(Tx) CK high to STXD valid from high impedance

—

15.0

SS19

SS1

SS2

SS4

SS3

SS5

SS6

SS8

SS10

SS12

SS14

SS18

SS15

SS17

SS16

SS43

SS42

Note: SRXD input in synchronous mode only

TXC

(Output)

TXFS (wl)

(Output)

TXFS (bl)

(Output)

RXD

(Input)

TXD

(Output)

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