USB7252P datasheet(18/64 Pages) MICROCHIP

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USB7252P

DS00003561A-page 18



2018 - 2020 Microchip Technology Inc.

Note 3-12

Configuration strap values are latched on Power-On Reset (POR) and the rising edge of

RESET_N

(external chip reset). Configuration straps are identified by an underlined symbol name. Signals that

function as configuration straps must be augmented with an external resistor when connected to a

load. For additional information, refer to Section 3.3, Configuration Straps and Programmable

Functions.

Note 3-13

Pin use is mandatory. Cannot be left unused.

3.3

Configuration Straps and Programmable Functions

Configuration straps are multi-function pins that are used during Power-On Reset (POR) or external chip reset

(

RESET_N) to determine the default configuration of a particular feature. The state of the signal is latched following

deassertion of the reset. Configuration straps are identified by an underlined symbol name. This section details the var-

ious device configuration straps and associated programmable pin functions.

Battery Charging

Configuration

Strap

CFG_BC_EN

I/O12

Battery Charging Configuration Strap.

This configuration strap controls the number

of BC 1.2 enabled downstream ports. See

Note 3-13.

Note 3-11

Mandatory if external SPI

memory is not used for

firmware e xe cu tion . If

external SPI memory is

us ed

fo r

firmwa re

ex ec utio n,

the n

configuration strap resistor

should be omitted.

Mandatory

Note 3-12

Device Mode

Configuration

Straps 3-1

CFG_STRAP[3:1]

Device Mode Configuration Straps 3-1.

These configuration straps are used to

select the device’s mode of operation. See

Note 3-13.

Mandatory

Note 3-12

Power/Ground

+3.3V I/O Power

Supply Input

VDD33

+3.3 V power and internal regulator input.

Mandatory

Note 3-12

Digital Core

Power Supply

Input

VCORE

Digital core power supply input.

Mandatory

Note 3-12

Ground

VSS

Common ground.

This exposed pad must be connected to the

ground plane with a via array.

Mandatory

Note 3-12

Note:

The system designer must guarantee that configuration straps meet the timing requirements specified in

Section 9.6.2, Power-On and Configuration Strap Timing and Section 9.6.3, Reset and Configuration Strap

Timing. If configuration straps are not at the correct voltage level prior to being latched, the device may

capture incorrect strap values.

TABLE 3-1:

PIN DESCRIPTIONS (CONTINUED)

Name

Symbol

Buffer

Type

Description

If Unused

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