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26HS01GTAM03 Scheda tecnica(PDF) 51 Page - Infineon Technologies AG

Il numero della parte 26HS01GTAM03
Spiegazioni elettronici  256Mb/512Mb/1Gb SEMPER??Flash HYPERBUS??interface, 1.8V/3.0V
PDF  166 Pages
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Produttore elettronici  INFINEON [Infineon Technologies AG]
Homepage  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

26HS01GTAM03 Scheda tecnica(HTML) 51 Page - Infineon Technologies AG

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002-12337 Rev. *Y
2022-01-18
256Mb/512Mb/1Gb SEMPER™ Flash
HYPERBUS™ interface, 1.8V/3.0V
Features
Figure 34
Host polling sequence for configuration corruption detection (x1 Legacy SPI)
4.6.4.1
Configuration corruption detection related registers
Table 38
Configuration corruption detection related registers and transactions
Related registers
(see Section 5.3 Legacy (x1) SPI registers on page 106)
Related SPI transactions
(see Table 122 on page 137)
Status Register 1 Volatile (STR1V)
All 1S-1S-1S Transactions
Power-Up
Read Status Register 1
Status Register 1
= 0x00?
&
Any Read Identification Transaction =
Successful
Device
Ready
Yes
No
Clear Status Register 1
Configure the Device by Updating All
Nonvolatile Registers
Device
Ready
Change Host Interface to Default
Flash Configuration
Corruption Detected
Status Register 1 = 0x41
Power-Up
Read Status Register 1
Status Register 1
= 0x00?
&
Any Read Identification Transaction =
Successful
Device
Ready
Yes
No
Clear Status Register 1
Configure the Device by Updating All
Nonvolatile Registers
Device
Ready
Change Host Interface to Default
Flash Configuration
Corruption Detected
Status Register 1 = 0x41
[21]
Note
21. As soon as first Write Any Register transaction updates the Nonvolatile Status register or Configuration register, all remaining nonvolatile status and
configuration registers go back to the predefined state (STR1N = 0x00, CFR1N = 0x00, CFR2N = 0x00, CFR3N = 0x00, CFR4N = 0x00). It is recommended
to initiate SafeBoot recovery operation by configuring the Address byte length and latency followed by rest configurations.



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