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FS5502 Scheda tecnica(PDF) 10 Page - NXP Semiconductors |
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FS5502 Scheda tecnica(HTML) 10 Page - NXP Semiconductors |
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10 / 113 page  NXP Semiconductors FS5502 High voltage PMIC with multiple SMPS and LDO aaa-033199 From VPRE ON SLOT_0 To NORMAL_M tslot SLOT_1 tslot SLOT_2 tslot SLOT_3 tslot SLOT_4 tslot SLOT_5 tslot SLOT_6 tslot Figure 5. Power sequencing (VREGx PWR_UP) Each regulator is assigned to a SLOT by OTP configuration using OTP_VB1S[2:0] for BUCK1, OTP_VB3S[2:0] for BUCK3, and OTP_LDO1S[2:0] for LDO1. The different soft start duration of the BUCKs and the LDO should be considered in the SLOT assignment to achieve the correct sequence. FS5502 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 27 October 2021 10 / 113 |
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