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FS5502 Scheda tecnica(PDF) 11 Page - NXP Semiconductors |
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FS5502 Scheda tecnica(HTML) 11 Page - NXP Semiconductors |
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11 / 113 page  NXP Semiconductors FS5502 High voltage PMIC with multiple SMPS and LDO aaa-033200 VSUP1,2 VSUP > VSUP_uvh WAKE12VIH VBOS_uvh VPRE_uvh and VPRE_soft_start complete 250 µs 250 µs WAKE1 or WAKE2 VBOS VPRE SLOT_0 SLOT_1 SLOT_2 SLOT_6 PGOOD RSTB Figure 6. Power up sequence example The FS5502_OTP_Mapping file used to generate the OTP configuration of the device draws the power up sequence of an OTP configuration in the OTP_conf_summary sheet. 8.5 Debug mode The FS5502 enter in Debug mode with the sequence described in Figure 7: 1. DBG pin = VDBG and VSUP > VSUP_UVH 2. WAKE1 or WAKE2 > WAKE12VIH VDBG and VSUP can come up at the same time as long as WAKE1 or WAKE2 comes up the last. FS5502 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 27 October 2021 11 / 113 |
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