USB7016 datasheet(17/60 Pages) MICROCHIP

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DS00003740B-page 17

USB7016

Note 3-9

Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N

(external chip reset). Configuration straps are identified by an underlined symbol name. Signals that

function as configuration straps must be augmented with an external resistor when connected to a

load. For additional information, refer to Section 3.3, Configuration Straps and Programmable

Functions.

Note 3-10

Pin use is mandatory. Cannot be left unused.

3.3

Configuration Straps and Programmable Functions

Configuration straps are multi-function pins that are used during Power-On Reset (POR) or external chip reset

(RESET_N) to determine the default configuration of a particular feature. The state of the signal is latched following

deassertion of the reset. Configuration straps are identified by an underlined symbol name. This section details the var-

ious device configuration straps and associated programmable pin functions.

3.3.1

PORT DISABLE CONFIGURATION (PRT_DIS_P[6:1] / PRT_DIS_M[6:1])

The PRT_DIS_P[6:1] / PRT_DIS_M[6:1] configuration straps are used in conjunction to disable the related port (6-1)

For PRT_DIS_Px (where x is the corresponding port 6-1):

0 = Port x D+ Enabled

1 = Port x D+ Disabled

For PRT_DIS_Mx (where x is the corresponding port 6-1):

0 = Port x D- Enabled

1 = Port x D- Disabled

Device Mode

Configuration

Straps 3-1

CFG_STRAP[3:1]

Device Mode Configuration Straps 3-1.

These configuration straps are used to

select the device’s mode of operation. See

Note 3-9.

Mandatory

Note 3-8

Power/Ground

+3.3V I/O Power

Supply Input

VDD33

+3.3 V power and internal regulator input.

Mandatory

Note 3-8

Digital Core

Power Supply

Input

VCORE

Digital core power supply input.

Mandatory

Note 3-8

Ground

VSS

Common ground.

This exposed pad must be connected to the

ground plane with a via array.

Mandatory

Note 3-8

Note:

The system designer must guarantee that configuration straps meet the timing requirements specified in

Section 9.6.2, Power-On and Configuration Strap Timing and Section 9.6.3, Reset and Configuration Strap

Timing. If configuration straps are not at the correct voltage level prior to being latched, the device may

capture incorrect strap values.

Note:

Both PRT_DIS_Px and PRT_DIS_Mx (where x is the corresponding port) must be tied to 3.3 V to disable

the associated downstream port. Disabling the USB 2.0 port will also disable the corresponding USB 3.0

port.

TABLE 3-1:

PIN DESCRIPTIONS (CONTINUED)

Name

Symbol

Buffer

Type

Description

If Unused

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