SiC401A, SiC401BCD

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Vishay Siliconix

S20-0483-Rev. E, 29-Jun-2020

21

Document Number: 63835

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

load release), and a 15 A load release, the required

capacitance is shown by the next equation.

During the load release time, the voltage cross the inductor

di/dt in the inductor. If the load dI/dt is not much faster than

the dI/dt of the inductor, then the inductor current will tend

to track the falling load current. This will reduce the excess

inductive energy that must be absorbed by the output

capacitor; therefore a smaller capacitance can be used.

The following can be used to calculate the needed

Peak inductor current is shown by the next equation.

Example

This would cause the output current to move from 15 A to

0 A in 4 μs, giving the minimum output capacitance

requirement shown in the following equation.

compared to 316 μF based on a worst case load release. To

meet the two design criteria of minimum 316 μF and

maximum 10.2 mW ESR, select one capacitor of 330 μF and

9 mW ESR.

Stability Considerations

Unstable operation is possible with adaptive on-time

controllers, and usually takes the form of double-pulsing or

ESR loop instability.

Double-pulsing occurs due to switching noise seen at the

FB input or because the FB ripple voltage is too low. This

causes the FB comparator to trigger prematurely after the

250 ns minimum off-time has expired. In extreme cases the

noise can cause three or more successive on-times.

Double-pulsing will result in higher ripple voltage at the

output, but in most applications it will not affect operation.

This form of instability can usually be avoided by providing

the FB pin with a smooth, clean ripple signal that is at least

of the output capacitors. It is also imperative to provide a

proper PCB layout as discussed in the Layout Guidelines

section.

Another way to eliminate doubling-pulsing is to add a small

(~ 10 pF) capacitor across the upper feedback resistor, as

shown in Fig. 13. This capacitor should be left unpopulated

until it can be confirmed that double-pulsing exists. Adding

eliminate the problem. An optional connection on the PCB

should be available for this capacitor.

Fig. 13 - Capacitor Coupling to FB Pin

ESR loop instability is caused by insufficient ESR. The

details of this stability issue are discussed in the ESR

Requirements section. The best method for checking

stability is to apply a zero-to-full load transient and observe

the output voltage ripple envelope for overshoot and ringing.

Ringing for more than one cycle after the initial step is an

indication that the ESR should be increased.

ESR Requirements

A minimum ESR is required for two reasons. One reason is

to generate enough output ripple voltage to provide

double-pulsing.

The second reason is to prevent instability due to insufficient

ESR. The on-time control regulates the valley of the output

ripple voltage. This ripple voltage is the sum of the two

voltages. One is the ripple generated by the ESR, the other

is the ripple due to capacitive charging and discharging

during the switching cycle. For most applications the

minimum ESR ripple voltage is dominated by the output

capacitors, typically SP or POSCAP devices. For stability

the ESR zero of the output capacitor should be lower than

approximately one-third the switching frequency. The

formula for minimum ESR is shown by the following

1 µH (10 +

1

2

Rate of change of load current =

dt

L x

-

x dt

dt

=

2.5 A

1 µs

1 µH x

-

x 1 µs

2 (1.65 - 1.5)

12.215

1.5

10

2.5

To FB pin