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ADPA7008AEHZ-R7 Scheda tecnica(PDF) 6 Page - Analog Devices

Il numero della parte ADPA7008AEHZ-R7
Spiegazioni elettronici  20 GHz to 54 GHz, GaAs, pHEMT, MMIC, 31 dBm (1 W) Power Amplifier
PDF  28 Pages
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

ADPA7008AEHZ-R7 Scheda tecnica(HTML) 6 Page - Analog Devices

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Data Sheet
ADPA7008
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
analog.com
Rev. 0 | 6 of 28
Figure 2. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 2, 12, 13
VDD1 to VDD4 Drain Biases for the Amplifier. External bypass capacitors of 4.7 µF, 0.01 µF, and 100 pF are required for these pins. See Figure 9 for the
interface schematic.
3, 5, 9, 11
NIC
Not Internally Connected. The NIC pins have no internal connections.
4, 10
VGG1, VGG2
Amplifier Gate Controls. External bypass capacitors of 4.7 µF, 0.01 µF, and 100 pF are required for these pins. Adjust VGG1 from −1.5 V to
−0.4 V to achieve the desired IDQ. See Figure 7 for the interface schematic .
6, 8, 15, 17
GND
Ground Pins. Connect the GND pins to RF and dc ground.
7
RFIN
RF Signal Input. The RFIN pin is ac-coupled and matched to 50 Ω. See Figure 6 for the interface schematic.
14
VDET
Detector Diode Used for Measuring the RF Output Power. Detection via the VDET pin requires the application of a dc bias voltage
through an external series resistor. Used in combination with VREF, the difference detector voltage, VREF − VDET, is a temperature
compensated dc voltage proportional to the RF output power (POUT). See Figure 5 for the interface schematic.
16
RFOUT
RF Signal Output. The RFOUT pin is ac-coupled and matched to 50 Ω. See Figure 8 for the interface schematic.
18
VREF
Reference Diode Voltage. Use the VREF pin for temperature compensation of the VDET RF POUT measurements. Used in combination
with VDET, this voltage provides temperature compensation to the VDET RF POUT measurements. See Figure 4 for the interface
schematic.
EPAD
Exposed Pad. The exposed pad must be connected to RF and dc ground
INTERFACE SCHEMATICS
GND
Figure 3. GND Interface Schematic
VREF
Figure 4. VREF Interface Schematic
VDET
Figure 5. VDET Interface Schematic
RFIN
Figure 6. RFIN Interface Schematic
VGG1,
VGG2
Figure 7. VGG1, VGG2 Interface Schematic
RFOUT
Figure 8. RFOUT Interface Schematic
VDD1 TO VDD4
Figure 9. VDD1 to VDD4 Interface Schematic



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