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BLC10G22LS-240PVT Scheda tecnica(PDF) 4 Page - Ampleon Netherlands B.V. |
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BLC10G22LS-240PVT Scheda tecnica(HTML) 4 Page - Ampleon Netherlands B.V. |
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4 / 17 page ![]() BLC10G22LS-240PVT All information provided in this document is subject to legal disclaimers. © Ampleon Netherlands B.V. 2017. All rights reserved. Product data sheet Rev. 2 — 24 May 2017 4 of 17 BLC10G22LS-240PVT Power LDMOS transistor 7.2 Impedance information [1] ZS and ZL defined in Figure 1. [2] at 3 dB gain compression. Table 8. Typical impedance Measured load-pull data per section; IDq = 800 mA; VDS = 28 V; pulsed CW (tp = 100 s; =10 %). f ZS [1] ZL [1] PL [2] D [2] Gp [2] (MHz) ( ) ( ) (W) (%) (dB) Maximum power load 2110 4.0 j9.8 2.4 j6.2 201.1 59.1 16.3 2140 4.7 j10.7 2.4 j6.2 205.1 59.3 16.4 2170 6.0 j10.8 2.2 j6.4 205.3 60.1 16.7 Maximum drain efficiency load 2110 4.0 j9.8 3.1 j4.4 164.7 67.8 18.1 2140 4.7 j10.7 3.1 j4.3 163.3 67.4 18.4 2170 6.0 j10.8 2.8 j4.5 163.0 67.2 18.4 Fig 1. Definition of transistor impedance 001aaf059 drain ZL ZS gate |
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