SWCS049G datasheet(122/144 Pages) TI

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TPS65911

SWCS049S – JUNE 2010 – REVISED AUGUST 2018

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Applications, Implementation, and Layout

7.2.1

Design Requirements

For a typical application shown in Figure 7-1, Table 7-1 lists the primary design parameters of the power

resources.

(1)

Value is dependent on external FETs.

Table 7-1. Design Parameters

DESIGN PARAMETER

VALUE

Supply voltage

2.7 V to 5.5 V

VDD1 voltage

1 V

VDD1 current

Up to 1.5 A

VDD2 voltage

1.35 V

VDD2 current

Up to 1.5 A

VDDCtrl voltage

1 V

VDDCtrl current

See (1)

VIO voltage

3.3 V

VIO current

Up to 1.1 A

LDO1 voltage

1.8 V

LDO1 current

Up to 320 mA

LDO2 voltage

1.8 V

LDO2 current

Up to 320 mA

LDO3 voltage

1.8 V

LDO3 current

Up to 200 mA

LDO4 voltage

1.8 V

LDO4 current

Up to 50 mA

LDO5 voltage

3.3 V

LDO5 current

Up to 300 mA

LDO6 voltage

3.3 V

LDO6 current

Up to 300 mA

LDO7 voltage

3.3 V

LDO7 current

Up to 300 mA

LDO8 voltage

3.3 V

LDO8 current

Up to 300 mA

7.2.2

Detailed Design Procedure

7.2.2.1

External Component Recommendation

For crystal oscillator components, see Section 5.10. If RTC domain is expected to be maintained after

shutdown, VCC7 must have enough capacitance to make sure that when supply is switched off, voltage

does not fall at a rate faster than 10 mV/ms. This makes sure that RTC domain data is maintained.

Table 7-2. External Component Recommendation

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

POWER REFERENCES

VREF filtering capacitor (CO(VREF))

Connected from VREF to REFGND

100

VDD1 SMPS

Input capacitor (CI(VCC1))

X5R or X7R dielectric

µF

Output filter capacitor (CO(VDD1))

X5R or X7R dielectric

µF

CO filter capacitor ESR

ƒ = 3 MHz

300

mΩ

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