SWCS049G datasheet(126/144 Pages) TI

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OUT

OUT max

IND

126

TPS65911

SWCS049S – JUNE 2010 – REVISED AUGUST 2018

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Applications, Implementation, and Layout

7.2.2.2.4 Selecting FETs

This controller is designed to drive two n-channel MOSFETs. Typically, lower RDS(on) values are better for

improving the overall efficiency of the controller, however higher gate-charge thresholds result in lower

efficiency so these two values must be balanced for optimal performance. As the RDS(on) for the low-side

FET decreases, the minimum current limit increases. Therefore, make sure the appropriate values are

selected for the FETs, inductor, output capacitors, and current limit resistor. The Texas Instruments'

CSD87330Q3D device is a recommended for the controller, depending on the required maximum current.

7.2.2.2.5 Bootstrap Capacitor

To make sure the internal high-side gate drivers are supplied with a stable low-noise supply voltage, a

capacitor must be connected between the SW pin and the VBST pin. TI recommends placing ceramic

capacitors with a value of 0.1 μF for the controller. TI recommends reserving a small resistor in series with

the bootstrap capacitor in case the turnon and turnoff of the FETs must be slowed to decrease voltage

ringing on the switch node, which is a common practice for controller design.

7.2.2.2.6 Selecting Input Capacitors

Because of the nature of the switching controller with a pulsating input current, a low ESR input capacitor

is required for the best input-voltage filtering and also to minimize the interference with other circuits

caused by high input-voltage spikes. For the controller, a typical 1-μF capacitor can be used for the V5IN

pin to support the transients on the driver. For the FET input, 40 μF of input capacitance is recommended

for most applications. To achieve the low ESR requirement, a ceramic capacitor is recommended.

However, the voltage rating and DC-bias characteristic of ceramic capacitors must be considered. For

better input-voltage filtering, the input capacitor can be increased without any limit. TI recommends placing

a ceramic capacitor as near as possible to the FET across the respective VSYS and PGND pins of the

FETs.

NOTE

Use the correct value for the ceramic capacitor capacitance after derating to achieve the

recommended input capacitance.

7.2.2.3

Converter Design Procedure

7.2.2.3.1 Selecting the Inductor

An inductor must be placed between the external FETs and the output capacitors. Together, the inductor

and output capacitors form a double pole in the control loop that contributes to stability. In addition, the

inductor is directly responsible for the output ripple, efficiency, and transient performance. As the

inductance increases, the ripple current decreases, which typically results in an increase in efficiency.

However, with an increase in inductance, the transient performance decreases. Finally, the selected

inductor must be rated for the appropriate saturation current, core losses, and DC resistance (DCR).

NOTE

The internal parameters for the converters are optimized for a 2.2-µH inductor, however

using other inductor values is possible as long as they are carefully selected and thoroughly

tested.

Use Equation 5 to calculate the recommended inductance for the converter.

where

•

VOUT is the typical output voltage.

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