| Motore di ricerca datesheet componenti elettronici |
|
RZ/T2M Scheda tecnica(PDF) 105 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
RZ/T2M Scheda tecnica(HTML) 105 Page - Renesas Technology Corp |
|
105 / 127 page ![]() Table 2.36 xSPI timing Parameter Symbol 1.8 V 3.3 V Unit Reference figure Min. Max. Min. Max. Cycle time SDR tPERIOD 7.5 — 13.3 — ns Figure 2.73 DDR 10.0 — 13.3 — ns Clock output slew rate tSRck 0.75/0.56*2 — 0.56 — V/ns Clock Duty cycle distortion tCKDCD 0.0 tPERIOD × 0.05 0.0 tPERIOD × 0.05 ns Clock Minimum Pulse width tCKMPW tPERIOD × 0.45 — tPERIOD × 0.45 — ns Differential clock crossing voltage VOX(AC) 0.4 × VCC18 0.6 × VCC18 — — V DS Duty cycle distortion tDSDCD 0.0 tPERIOD × 0.04 0.0 tPERIOD × 0.04 ns DS Minimum Pulse width tDSMPW tPERIOD × 0.41 — tPERIOD × 0.41 — ns Data input/output slew rate tSR 0.75/0.56*2 — 0.56 — V/ns Data input setup time (to CK) SDR tSU 2.0 — 2.4 — ns Figure 2.74 Data input hold time (to CK) tH 1.0 — 1.0 — ns Data output delay time tOD — 1.0*3 — 1.4*3 ns Data output hold time tOH -1.0 — -2.3 — ns Data output buffer off time tBOFF -1.0 — -2.3 — ns Data input setup time (to DS) DDR*1 *3 tSU -0.8 — -0.8 — ns Figure 2.75, Figure 2.76 Data input hold time (to DS) tH tPERIOD × 0.41 - 0.8 — tPERIOD × 0.41 - 0.8 — ns Data output setup time (to CK) tSUO 1.0 — 1.0 — ns Data output hold time (to CK) tHO 1.0 — 1.0 — ns CS Low to Clock High tCSLCKH 6.0/8.0*2 *4 — 8.0*4 — ns Figure 2.74 to Figure 2.76 Clock Low to CS High tCKLCSH 6.0/8.0*2 — 8.0 — ns CS High time tCSTD 1 16 1 16 tPERIOD DS Low to CS High tDSLCSH 6.0/8.0*2 — 10.6 — ns Figure 2.77 CS High to DS Tri-State tCSHDST 0.0 tPERIOD 0.0 tPERIOD ns CS Low to DS Low tCSLDSL 0.0 — 0.0 — ns DS Tri-State to CS Low tDSTCSL 0.0 — 0.0 — ns Note 1. The DS shift setting (WRAPCFG.DSSFTCSx[4:0]) is 01000b for xSPI200. Note 2. Specification at 133 MHz / Specification at 100 MHz Note 3. These are values when the OEN assertion is extended in the Output Enable Asserting extension bit (COMCFG.OEASTEX = 1). Note 4. These are the values when the CS assertion is extended in the CS asserting extension bit (LIOCFGCSn.CSASTEX = 1). RZ/T2M Datasheet 2. Electrical Characteristics R01DS0383EJ0100 Rev.1.00 Mar 22, 2022 Page 105 of 127 |
|
Link URL |
| Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | Collegamento alla scheda tecnica | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |