HT48C10 datasheet(21/59 Pages) HOLTEK

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Watchdog timer

If the internal WDT oscillator (RC oscillator

with a period of 78

µs normally) is selected, it is

first divided by 256 (8 stages) to derive a nomi-

nal time-out period of about 20ms. This time-

out period may vary with temperature, VDD,

and process variations. By invoking the WDT

prescaler, longer time-out periods can be real-

ized. Writing data to WS2, WS1, and WS0 (bit

2,1,0 of the WDTS) can lead to different time-

out periods. If the values of WS2, WS1, and WS0

all equal to 1, the division ratio is up to 1:128,

and the maximum time-out period is 2.6 sec-

onds.

But if the WDT oscillator is disabled, the WDT

clock may still come from the instruction clock

and operate in the same manner except that in

the HALT state the WDT may stop counting

and lose its protecting purpose. In this situation

the logic can be restarted by external logic. The

high nibble and bit 3 of the WDTS are reserved

for user defined flags, and the programmer may

use these flags to indicate some specified status.

WS2

WS1

WS0

Division Ratio

000

1:1

001

1:2

010

1:4

011

1:8

1:16

1:32

1:64

1:128

WDTS Register

If the device operates in a noisy environment,

using the on-chip RC oscillator (WDT OSC) is

strongly recommended, since the HALT will ter-

minate the system clock.

The overflow of WDT under normal operation

can initialize “chip reset” and set the status bit

TO. But in the HALT mode, the overflow will

initialize a “warm reset”, and only the PC and

SP are reset to zero. To clear the contents of

WDT (the WDT prescaler included), three

methods can be adopted, i.e., external reset (a

low level to RES), software instruction(s), and a

HALT instruction. The software instruction(s)

consists of CLR WDT and the other set — CLR

WDT1 and CLR WDT2. Of these two types of

instructions, only one type can be active de-

pending on mask option — “CLR WDT times

selection option”. If the “CLR WDT” is chosen

(i.e., CLRWDT times equal one), any execution

of the CLR WDT instruction will clear the WDT.

In the case that the “CLR WDT1” and “CLR

WDT2” are chosen (i.e., CLRWDT times equal

two), these two instructions should be executed

to clear the WDT; otherwise, the WDT may

reset the chip due to time-out.

Power down operation – HALT

The HALT mode is initialized by the HALT

instruction and results in the following.

• The system oscillator turns off but the WDT

oscillator keeps running (if the WDT oscillator

is selected).

• The contents of the on–chip RAM and regis-

ters remain unchanged.

• The WDT and WDT prescaler are cleared and

recount (if the WDT clock comes from the

WDT oscillator).

• All I/O ports maintain their original status.

• The PD flag is set and the TO flag is cleared.

The system can quit the HALT mode by exter-

HT48CXX/HT48RXX

25th May ’99

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