ADP5140WACCZ-R7 datasheet(46/128 Pages) AD

46 / 128 page

ADP5140

Data Sheet

Rev. 0 | Page 46 of 128

POWER-UP AND POWER-DOWN SEQUENCES

All regulators in the ADP5140 integrate a soft start circuit to

reduce the inrush current on the input voltage during startup.

Power-Up Sequence

A fixed power-up sequence, as shown in Figure 89, is applied to

all regulators when enabled. There is a typical 3 ms (tD) delay

for the ADP5140 initial and self test time, and tDR1 or tDR2 delays

between each rail.

Regulator 10 and Regulator 11 power up at the same time.

Regulator 12 does not power up until both Regulator 10 and

Regulator 11 are above the fault low threshold followed by thee

tDR2 delay time.

The SEQ pin controls the power-up sequence. When the

Regulator 1 powers up, the other power rails on the ADP5140

do not ramp up until the SEQ pin goes high.

Regulator 3 does not power up until Regulator 1 is above the

fault low threshold followed by the tDR1 delay time, and the

SEQ pin is high.

The RESET pin does not pull high until all of the following

conditions are met and are followed by a tHOLD delay:

•

Regulator 1 is in regulation.

•

Regulator 2 is in regulation.

•

Regulator 5 is in regulation.

•

Regulation 10 is in regulation.

•

Regulation 11 is in regulation.

•

Regulation 12 is in regulation.

•

SEQ is high.

•

No other system fault event is mapped on the RESET pin

occurs.

The FAULT and STATUS pins keep low until all power rails are

above the fault low threshold and the RESET pin is released.

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