ADP5140WACCZ-R7 datasheet(49/128 Pages) AD

49 / 128 page

Data Sheet

ADP5140

Rev. 0 | Page 49 of 128

Figure 91 shows the SPI bit frame that has two phases. The first

phase is the instruction phase that includes the command,

address, and reserve. The second phase is the data phase that

includes the data and cyclic redundancy check (CRC).

CMD

ADDR

RSV

DATA

INSTRUCTION PHASE

CRC

DATA PHASE

Figure 91. SPI Bit Frame

Command (CMD)

CMD is an 8-bit field that indicates the action that the host

wants to perform, as shown in Table 32.

Table 32. Command Byte Description

Bit(s)

Description

0: write operation

1: read operation

0: broadcast disable

1: broadcast enable

Reserved

0: little Endian

1: big Endian (default)

0: MSB first (default)

1: LSB first

[2:1]

Device index

0: write operation

1: read operation

Bit 7 and Bit 0 in this field indicate whether the host wants to

perform a write (00) or a read (11) operation, respectively. Note

that 01 and 10 are invalid values.

Bit 1 and Bit 2 in this field indicate the device index of the

ADP5140 to which the host wants to communicate. The device

index is determined by the MODE pin configuration in Table 27.

Bit 3 and Bit 4 in this field indicate the SPI communication

command mode of the ADP5140 with big Endian and MSB

first as the default. The command mode is programmable

through the SPI IF_CFGA register. The ADP5140 supports the

following four types of command modes:

•

Mode 0: little Endian and MSB first.

•

Mode 1: little Endian and LSB first.

•

Mode 2: big Endian and MSB first (default).

•

Mode 3: big Endian and LSB first.

Note that if the broadcast feature is enabled (Bit 6 in CMD is

set to 1), any device with the CS pin pulled low is under

communication despite the device index value (Bit 1 and Bit 2

in CMD).

Address (ADDR)

ADDR is a 2-byte field that contains the register address the

host wants to access. The ADDR field duration is 16 SCK cycles.

Refer to the SPI Register Map section for more information.

Reserved (RSV)

RSV is a 1-byte field reserved by the ADP5140. The RSV field

duration is eight SCK cycles.

Data (DATA)

DATA is a 4-byte field that contains the data to transfer. The

DATA field duration is 32 SCK cycles.

CRC

The ADP5140 uses the CRC field to detect data communication

errors in each SPI frame. The CRC field in the SPI frame is a

16-bit field containing the computed CRC value.

CRC is always sent MSB first and spans over the CMD, ADDR,

RSV, and DATA fields.

The default polynomial used to calculate CRC is x16 + x15 + x12 +

x7 + x6 + x4 + x3 + 1 (0x90D9), and the default initial seed value to

calculate CRC is 0x5555. Both the polynomial and initial seed

values can be configured in the SPI_CRC_PARAM register.

Figure 92 and Figure 93 show the time sequence of SPI write

and read operations.

C7:C0

R7:R0

A7:A0

A15:A8

D7:D0

D15:D8

D23:D16

D31:D24

CRC15:CRC0

MOSI

COMMAND

ADDRESS

RESERVED

DATA

CRC

HIGH IMPEDANCE

MISO

Figure 92. SPI Write Operation

C7:C0

MOSI

COMMAND

ADDRESS

RESERVED

DATA

CRC

MISO

R7:R0

A7:A0

A15:A8

D7:D0

D15:D8

D23:D16

D31:D24

CRC15:CRC0

Figure 93. SPI Read Operation

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