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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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TC35679FSG Scheda tecnica(PDF) 12 Page - Toshiba Semiconductor |
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TC35679FSG Scheda tecnica(HTML) 12 Page - Toshiba Semiconductor |
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12 / 45 page  TC35679FSG-002 2018-01-17 12 3. System Configuration 3.1. Block Diagram Figure 3-1 shows block diagram of TC35679. TC35679 is powered by single voltage between 1.8 V and 3.6 V. The chip has built-in DCDC and LDO requiring external capacitors. It uses 26 MHz reference clock and 32.768 kHz sleep clock. External memory Interface is SPI or I2C, and host CPU interface is UART. RF Block 26MHz X’tal ClockGen/ Clock Management RF PLL Power Management Controller VDD 1.8～ 3.6V TC35679 Baseband Block UART 2ch HOST I/F SPI/ I2C PWM 4ch GPIO ADC 6ch Modem ARM® Cortex®-M0 Mask ROM RAM (BackUp) Selector VDDCORE2 Ref VDD 32kHz X’tal DCDC LDO Level Detector Figure 3-1 Example of the TC35679 internal block diagram and the peripheral components connection diagram VBAT 1.8 to 3.6 V VBAT |
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