STM32W108CB datasheet(110/278 Pages) STMICROELECTRONICS

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Serial interfaces

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Doc ID 16252 Rev 14

Characters received are stored in the receive FIFO. Receiving characters sets the RXNE bit

in the SCx_SPISR register, indicating that characters can be read from the receive FIFO.

Characters received while the receive FIFO is full are dropped, and the OVF bit in the

SCx_SPISR register is set. The receive FIFO hardware generates the OVR, but the DMA

marks a receive error, two conditions will clear the error indication: setting the appropriate

TXRST/RXRST bit in the SCx_DMACR register, or loading the appropriate DMA buffer after

it has unloaded.

To receive a character, you must transmit a character. If a long stream of receive characters

is expected, a long sequence of dummy transmit characters must be generated. To avoid

software or transmit DMA initiating these transfers and consuming unnecessary bandwidth,

the SPI serializer can be instructed to retransmit the last transmitted character or to transmit

a busy token (0xFF), which is determined by the RPTEN bit in the SCx_SPICR register. This

functionality can only be enabled or disabled when the transmit FIFO is empty and the

transmit serializer is idle, indicated by a cleared IDLE bit in the SCx_SPISR register.

Every time an automatic character transmission starts, a transmit underrun is detected as

there is no data in transmit FIFO, and the UDR bit in the SC2_ISR register is set. After

automatic character transmission is disabled, no more new characters are received. The

receive FIFO holds characters just received.

Note:

The Receive DMA complete event does not always mean the receive FIFO is empty.

The DMA Channels section describes how to configure and use the serial receive and

transmit DMA channels.

9.3.3

Interrupts

SPI master controller second level interrupts are generated by the following events:

●

Transmit FIFO empty and last character shifted out (depending on SCx_ICR, either the

0 to 1 transition or the high level of IDLE)

●

Transmit FIFO changed from full to not full (depending on SCx_ICR, either the 0 to 1

transition or the high level of TXE)

●

Receive FIFO changed from empty to not empty (depending on SCx_ICR, either the 0

to 1 transition or the high level of RXNE)

●

Transmit DMA buffer A/B complete (1 to 0 transition of TXAACK/TXBACK)

●

Receive DMA buffer A/B complete (1 to 0 transition of RXAACK/RXBACK)

●

Received and lost character while receive FIFO was full (receive overrun error)

●

Transmitted character while transmit FIFO was empty (transmit underrun error)

To enable CPU interrupts, set the desired interrupt bits in the SCx_IER register.

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