STM32W108CB datasheet(124/278 Pages) STMICROELECTRONICS

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Serial interfaces

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Doc ID 16252 Rev 14

9.8

Serial controller common registers

9.8.1

Serial controller interrupt status register (SCx_ISR)

Address offset: 0xA808 (SC1_ISR) and 0xA80C (SC2_ISR)

Reset value:

0x0000 0000

Reserved

TXUL

ODB

TXUL

ODA

RXUL

ODB

RXUL

ODA

NACK

CMD

FIN

BTF

BRF

UDR

OVR

IDLE

TXE

RXNE

Bit [31:15] Reserved, must be kept at reset value

Bit 14 PE: Parity error pending interrupt

This bit is set by hardware when a parity error occurs in receiver mode.

0: No parity error pending interrupt

1: Parity error pending interrupt

Note: Not used in SC2

Bit 13 FE: Framing error pending interrupt

This bit is set by hardware when a desynchronization or excessive noise is detected.

0: No framing error detected pending interrupt

1: Framing error pending interrupt

Note: Not used in SC2

Bit 12 TXULODB: DMA transmit buffer B unloaded pending interrupt

This bit is set by hardware when DMA load error is detected during transmission.

0: No DMA transmit buffer B unloaded error pending interrupt

1: DMA transmit buffer B unloaded pending interrupt

Bit 11 TXULODA: DMA transmit buffer A unloaded pending interrupt

This bit is set by hardware when DMA load error is detected during transmission.

0: No DMA transmit buffer A unloaded error pending interrupt

1: DMA transmit buffer A unloaded error pending interrupt.

Bit 10 RXULODB: DMA receive buffer B unloaded pending interrupt

This bit is set by hardware when DMA load error is detected during reception.

0: No DMA receive buffer B unloaded error pending interrupt

1: DMA receive buffer B unloaded error pending interrupt

Bit 9 RXULODA: DMA receive buffer A unloaded pending interrupt

This bit is set by hardware when DMA load error is detected during reception.

0: No DMA receive buffer A unloaded error pending interrupt

1: DMA receive buffer A unloaded error pending interrupt

Bit 8 NACK: I2C not acknowledge received pending interrupt

This bit is set by hardware when a NACK is received after a byte transmission.

0: No NACK detected pending interrupt

1: NACK detected pending interrupt

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