STM32W108CB datasheet(270/278 Pages) STMICROELECTRONICS

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Revision history

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Doc ID 16252 Rev 14

Revision history

Table 73.

Document revision history

Date

Revision

Changes

16-Sep-2009

Initial release.

21-Sep-2009

Modified document status to Preliminary Data.

24-Nov-2009

Major revision of Section 1.2: Overview on page 12 and Section 9:

Serial interfaces on page 105.

Added Section 2: Documentation conventions on page 14,

Section 4: Embedded memory on page 27 and Section 7: Integrated

voltage regulator on page 85.

01-Mar-2010

Updated Section 11.1.8: Calibration on page 224.

Added notes to Software reset on page 44, Section 9.6.1: Setup and

configuration on page 119 and Section 11: Analog-to-digital

converter on page 218.

Updated parameters and values in Table 48: General operating

conditions on page 242.

22-Sep-2010

Added Section 13.1: STM32W108 JTAG TAP connection on

page 239 and Section 6.4.5: Slow timer (MAC timer, Watchdog, and

Sleeptimer) control and status registers on page 60.

Added Total Tx current values for 24 MHz in Table 64: DC electrical

characteristics on page 254 and updated Figure 58: Transmit power

consumption on page 257.

20-Oct-2010

Updated Table 56: ADC module key parameters for 1 MHz sampling

and Table 57: ADC module key parameters for input buffer disabled

and 6 MHz sampling.

Added Table 58: ADC module key parameters for input buffer

enabled and 6MHz sampling.

Modified system wakeup time from deep sleep in Table 66: Non-RF

system electrical characteristics.

09-Dec-2010

Updated datasheet status to full datasheet.

29-Mar-2011

Added INT_SLEEPTMRFLAG, INT_SLEEPTMRCFG,

SLEEPTMR_CLKEN.

27-Jul-2011

Update for STM32W108CC and STM32W108CZ

30-Sep-2011

Added Note 2 in Section Figure 63.: UFQFPN48 7x7 mm pitch 0.5

package outline.

05-Dec-2011

Updated document title

Section 4.2: Flash memory: replaced 1000 with 10k write/erase

cycles.

Section 10.3.10: Timer x capture/compare enable register

(TIMx_CCER): updated names of bits 12, 8, 4, and 0.

Figure 51: ADC block diagram : added footnote1.

Section 11.1.4: Offset/gain correction: Added third bullet point about

the offset/gain corrected value; added HV buffer offset calculation for

STM32W108CC and STM32W108CZ devices.

Table 39: Typical ADC input configurations: added footnote 1.

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