STM32W108CB datasheet(273/278 Pages) STMICROELECTRONICS

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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

Revision history

Doc ID 16252 Rev 14

273/278

03-Sep-2012

(continued)

Renamed the constituent bits of the following registers throughout

document:

TIMx_CR1

TIMx_CR2

TIMx_SMCR

TIMx_EGR

TIMx_CCMR1

TIMx_CCMR2

TIMx_CCER

TIMx_CNT

TIMx_PSC

TIMx_ARR

TIMx_CCR1

TIMx_CCR2

TIMx_CCR3

TIMx_CCR4

TIM1_OR

TIM2_OR

Renamed the following terms: OSC32A to OSC32_OUT, OSC32B to

OSC32_IN, OSC32K to LSE OSC, CLK32K to LSE, OSCRC to

LSI10K, CLK1K to LSI1K, OSCA to OSC_OUT, OSCB to OSC_IN,

OSC24M to HSE OSC, OSCHF to HSI, 24 MHz XTAL to 24 MHz

HSE OSC, 12 MHz RC to 12 MHz HSI RC, 10 kHz RC to 10 kHz LSI

RC, 32 kHz XTAL to 32 kHz HSE OSC

Updated terminology of Figure 6: System module block diagram and

Figure 7: Clocks block diagram.

Section 6.4.5: Replaced: ENABLE bit with EN, SLEEP_CONFIG with

SLPTMR_CR, COMP_A_H with CMPAH, COMP_A_L with CMPAL,

COMP_B_H with CMPBH, COMP_B_L with CMPBL.

Figure 10: Replaced SCx_I2CSTAT, SCx_I2CCTRL1, and

SCx_I2CCTRL2 with SCx_I2CSR, SCx_I2CCR1, and SCx_I2CCR2

respectively.

Section 10: replaced TMRx with TIMx, TIM_USR with USR, CCR1L

with CCR1[15:0], CCR1H with CCR1[31:16], CNT with TIMx_CNT,

CNT with CNT[15:0], CCR1 with TIMx_CCR1, TIMx_CC1R with

TIMx_CCR1, TIM_CCRx with TIMx_CCRy, TIM_CMS with

CMS[1:0], OCxREF with OCyREF, TIM_CCyIF with CCyIF,

TIM_SMCR with TIMx_SMCR, TIM_OC* with OCxy, and TIM_IC*

with ICxy.

GENERIC CHANGES

Updated “reserved” bit descriptions throughout document.

Removed all references to NVIC.

Removed all references to the INT_CFGSET register, INT_CFGCLR

Removed all non-defined asterisks.

SPECIFIC CHANGES

Section 1.2.1: updated selectable voltage ranges of ADC.

Added Section 4.1: Memory organization and memory map.

Added Section 4.3.3 and Section 4.3.4.

Table 73.

Document revision history (continued)

Date

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