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BT81X (815/6) Advanced Embedded Video Engine Datasheet

Version 1.0

Document No.: BRT_000220 Clearance No.: BRT#126

Figure 4-8 RGB Timing Waveforms

4.6 Miscellaneous Control

4.6.1

Backlight Control Pin

The backlight dimming control pin (BACKLIGHT) is a pulse width modulated (PWM) signal controlled by

two registers: REG_PWM_HZ and REG_PWM_DUTY. REG_PWM_HZ specifies the PWM output frequency,

the range is 250-10000 Hz. REG_PWM_DUTY specifies the duty cycle; the range is 0-128. A value of 0

means that the PWM is completely off and 128 means completely on.

The BACKLIGHT pin will output low when the DISP pin is not enabled (i.e. logic 0).

4.6.2

DISP Control Pin

The DISP pin is a general purpose output that can be used to enable, or reset the LCD display panel. The

pin is controlled by writing to Bit 7 of the REG_GPIO register, or bit 15 of REG_GPIOX.

4.6.3

General Purpose IO pins

The BT815/6 can be configured to use up to 4 GPIO pins. These GPIO pins are controlled by the

REG_GPIOX_DIR and REG_GPIOX registers. Alternatively the GPIO0 and GPIO1 pins can also be

controlled by REG_GPIO_DIR and REG_GPIO to maintain backward compatibility with the FT800/FT801.

When the QSPI is enabled in Quad mode, GPIO0/IO2 and GPIO1/IO3 pins are used as data lines of the

QSPI.

BT815Q-R Scheda tecnica(PDF) 29 Page - Bridgetek Pte Ltd.