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BT81X (815/6) Advanced Embedded Video Engine Datasheet

Version 1.0

Document No.: BRT_000220 Clearance No.: BRT#126

4.4 SPI NOR Flash Interface

The BT815/6 implements a SPI master to connect to external SPI NOR Flash. Graphics assets such as

Unicode fonts and images can be stored in the flash memory. The BT815/6 graphics engine can fetch

these graphics assets directly without going through external host MCU, thus significantly offloading the

host MCU from feeding display contents.

The BT815/6 supports various NOR flash memory device from different vendors such as Macronix,

Winbond, Micron, ISSI and Gigadevice. The interface will work at system clock speed (up to 72MHz) at 4

bit mode.

Figure 4-7 Flash Interface States

The register REG_FLASH_STATE indicates the state of the flash subsystem. At boot the flash state is

FLASH_STATE_INIT. After detection has completed flash is in state FLASH_STATE_DETACHED or

FLASH_STATE_BASIC, depending on whether an attached flash device was detected.

If no device is detected, then all SPI output signals are driven low.

When the host MCU calls CMD_FLASHFAST, the flash system attempts to go to full-speed mode, setting

state to FLASH_STATE_FULL.

At any time the user can call CMD_FLASHDETACH in order to disable flash communications. In the

detached state, commands CMD_FLASHSPIDESEL, CMD_FLASHSPITX and CMD_FLASHSPIRX can be used

to control the SPI bus.

If detached, the host MCU can call CMD_FLASHATTACH to re-establish communication with the flash

device.

Direct rendering of bitmaps from flash is only possible in FLASH_STATE_FULL. After modifying the

contents of flash, the MCU should clear the on-chip bitmap cache by calling CMD_CLEARCACHE.

4.5 Parallel RGB Interface

The RGB parallel interface consists of 29 signals - DISP, PCLK, VSYNC, HSYNC, DE, 8 signals each for R,

G and B.

A set of RGB registers configure the LCD operation and timing parameters.

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