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BT81X (815/6) Advanced Embedded Video Engine Datasheet

Version 1.0

Document No.: BRT_000220 Clearance No.: BRT#126

4.9.2

Internal Regulator and POR

The internal regulator provides power to the core circuit. A 47kΩ resistor is recommended to pull the

PD_N pin up to VCCIO1, together with a 100nF capacitor to ground in order to delay the internal

regulator powering up after the VCC and VCCIO are stable.

The internal regulator requires a compensation capacitor to be stable. A typical design requires a 4.7uF

capacitor between the VOUT1V2 and GND pins. Do not connect any other load to the VOUT1V2 pin.

The internal regulator will generate a Power-On-Reset (POR) pulse when the output voltage rises above

the POR threshold. The POR will reset all the core digital circuits.

It is possible to use the PD_N pin as an asynchronous hardware reset input. Drive PD_N low for at least

5ms and then drive it high will reset the BT815/6 chip.

Figure 4-12 Internal Regulator

4.9.3

Power Modes

When the supply to VCCIO and VCC is applied, the internal regulator is powered by VCC. An internal POR

pulse will be generated during the regulator power up until it is stable. After the initial power up, the

BT815/6 will stay in the SLEEP state. When needed, the host can set the BT815/6 to the ACTIVE state by

performing a SPI ACTIVE command. The graphics engine, the audio engine and the touch engine are only

functional in the ACTIVE state. To save power the host can send a command to put the BT815/6 into any

of the low power modes: STANDBY, SLEEP and POWERDOWN. In addition, the host is allowed to put the

BT815/6 in POWERDOWN mode by driving the PD_N pin to low, regardless of what state it is currently in.

Refer to Figure 4-13 for the power state transitions.

VCC

PD_N

VOUT1V2

VCC

GND

VCCIO1

10uF

100nF

GND

4.7uF

47k

BT815/6

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