AD7453BRT-R2 datasheet(13/20 Pages) AD

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AD7453

In applications with a slower SCLK, it may be possible to read

in data on each SCLK rising edge, i.e., the first rising edge of

SCLK after the

CS falling edge would have the leading zero

provided and the 15th SCLK edge would have DB0 provided.

Timing Example 1

Having FSCLK = 10 MHz and a throughput rate of 555 kSPS

gives a cycle time of

11 555 000

1 8

Throughput

A cycle consists of

SCLK

ACQ

12 5 1

1 8

()+=

Therefore if t2 = 10 ns, then

12 5 1 18

540

MHz

tns

ACQ

()+=

This 540 ns satisfies the requirement of 290 ns for tACQ.

From Figure 12, tACQ comprises

25 1

./ Ft

SCLK

QUIET

()++

where t8 = 35 ns. This allows a value of 255 ns for tQUIET, satis-

fying the minimum requirement of 60 ns.

MODES OF OPERATION

The mode of operation of the AD7453 is selected by controlling

the logic state of the

CS signal during a conversion. There are

two possible modes of operation, normal mode and power-down

mode. The point at which

CS is pulled high after the conversion

has been initiated determines whether the AD7453 will enter

the power-down mode. Similarly, if already in power-down,

controls whether the device will return to normal operation or

remain in power-down. These modes of operation are designed

to provide flexible power management options. These options

can be chosen to optimize the power dissipation/throughput rate

ratio for differing application requirements.

Normal Mode

This mode is intended for fastest throughput rate performance.

The user does not have to worry about any power-up times with

the AD7453 remaining fully powered up all the time. Figure 13

shows the general diagram of the operation of the AD7453 in

this mode. The conversion is initiated on the falling edge of

CS,

as described in the Serial Interface section. To ensure that the

part remains fully powered up,

CS must remain low until at least

10 SCLK falling edges have elapsed after the falling edge of

CS.

CS is brought high any time after the 10th SCLK falling edge,

but before the 16th SCLK falling edge, the part will remain pow-

ered up but the conversion will be terminated and SDATA will

go back into three-state. Sixteen serial clock cycles are required

to complete the conversion and access the complete conversion

result.

CS may idle high until the next conversion or may idle

low until sometime prior to the next conversion. Once a data

transfer is complete, i.e., when SDATA has returned to three-

state, another conversion can be initiated after the quiet time,

tQUIET, has elapsed by again bringing CS low.

SCLK

SDATA

4 LEADING ZEROS + CONVERSION RESULT

Figure 13. Normal Mode Operation

Power-Down Mode

This mode is intended for use in applications where slower

throughput rates are required; either the ADC is powered down

between each conversion, or a series of conversions may be

performed at a high throughput rate and the ADC is then powered

down for a relatively long duration between these bursts of

several conversions. When the AD7453 is in power-down mode,

SCLK

tQUIET

tCONVERT

345

tACQUISITION

12.5(1/FSCLK)

1/THROUGHPUT

10ns

Figure 12. Serial Interface Timing Example

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