AD7453BRT-R2 datasheet(14/20 Pages) AD

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AD7453

all analog circuitry is powered down. For the AD7453 to enter

power-down mode, the conversion process must be interrupted

by bringing

CS high anywhere after the second falling edge of

SCLK and before the tenth falling edge of SCLK, as shown in

Figure 14.

Once

CS has been brought high in this window of SCLKs, the

part will enter power-down and the conversion that was initi-

ated by the falling edge of

CS will be terminated and SDATA

will go back into three-state. The time from the rising edge of

CS to SDATA three-state enabled will never be greater than t

(see the Timing Specifications). If

CS is brought high before the

second SCLK falling edge, the part will remain in normal

mode and will not power down. This will avoid accidental

power-down due to glitches on the

CS line.

To exit this mode of operation and power up the AD7453

again, a dummy conversion is performed. On the falling edge of

CS the device will begin to power up, and will continue to

power up as long as

CS is held low until after the falling edge of

the 10th SCLK. The device will be fully powered up after 1

msec

has elapsed and, as shown in Figure 15, valid data will result

from the next conversion.

CS is brought high before the 10th falling edge of SCLK, the

AD7453 will again go back into power-down. This avoids

accidental power-up due to glitches on the

CS line or an inad-

vertent burst of eight SCLK cycles while

CS is low. So although

the device may begin to power up on the falling edge of

CS, it

will again power down on the rising edge of

CS as long as it

occurs before the 10th SCLK falling edge.

SCLK

SDATA

THREE–STATE

Figure 14. Entering Power-Down Mode

Power-Up Time

The power-up time of the AD7453 is typically 1

ms, which means

that with any frequency of SCLK up to 10 MHz, one dummy

cycle will always be sufficient to allow the device to power up.

Once the dummy cycle is complete, the ADC will be fully

powered up and the input signal will be acquired properly.

The quiet time, tQUIET, must still be allowed—from the point at

which the bus goes back into three-state after the dummy con-

version to the next falling edge of

CS.

When running at the maximum throughput rate of 555 kSPS,

the AD7453 will power up and acquire a signal within

±0.5 LSB in one dummy cycle. When powering up from the

power-down mode with a dummy cycle, as in Figure 15, the track-

and-hold, which was in hold mode while the part was powered

down, returns to track mode after the first SCLK edge the part

receives after the falling edge of

CS. This is shown as Point A in

Figure 15.

Although at any SCLK frequency one dummy cycle is sufficient

to power up the device and acquire VIN, it does not necessarily

mean that a full dummy cycle of 16 SCLKs must always elapse

to power up the device and acquire VIN fully; 1

ms will be suffi-

cient to power up the device and acquire the input signal.

For example, if a 5 MHz SCLK frequency was applied to the

ADC, the cycle time would be 3.2

ms (i.e., 1/(5 MHz) ¥ 16). In

one dummy cycle, 3.2

ms, the part would be powered up and

VIN acquired fully. However after 1

ms with a 5 MHz SCLK,

only five SCLK cycles would have elapsed. At this stage, the

ADC would be fully powered up and the signal acquired. So, in

this case, the

CS can be brought high after the 10th SCLK

falling edge and brought low again after a time, tQUIET, to ini-

tiate the conversion.

When power supplies are first applied to the AD7453, the ADC

may either power up in the power-down mode or normal

mode. Because of this, it is best to allow a dummy cycle to

elapse to ensure that the part is fully powered up before attempting

a valid conversion. Likewise, if the user wants the part to power

up in power-down mode, then the dummy cycle may be used to

ensure the device is in power-down mode by executing a cycle

such as that shown in Figure 14. Once supplies are applied to

the AD7453, the power-up time is the same as that when pow-

ering up from power-down mode. It takes approximately 1

to power up fully if the part powers up in normal mode. It is

not necessary to wait 1

ms before executing a dummy cycle to

ensure the desired mode of operation. Instead, the dummy

cycle can occur directly after power is supplied to the ADC. If

the first valid conversion is then performed directly after the

dummy conversion, care must be taken to ensure that adequate

acquisition time has been allowed.

As mentioned earlier, when powering up from the power-down

mode, the part will return to track mode upon the first SCLK

edge applied after the falling edge of

CS. However, when the

ADC powers up initially after supplies are applied, the track-and-

hold will already be in track mode. This means (assuming one

has the facility to monitor the ADC supply current) that if

the ADC powers up in the desired mode of operation and thus

a dummy cycle is not required to change mode, then neither is a

dummy cycle required to place the track-and-hold into track.

POWER VS. THROUGHPUT RATE

By using the power-down mode on the AD7453 when not

converting, the average power consumption of the ADC decreases

at lower throughput rates. Figure 16 shows how, as the throughput

rate is reduced, the device remains in its power-down state longer

and the average power consumption reduces accordingly. For

example, if the AD7453 is operated in continuous sampling mode

with a throughput rate of 100 kSPS and an SCLK of 10 MHz,

and the device is placed in the power-down mode between con-

versions, then the power consumption is calculated as follows:

Power dissipation during normal operation = 7.25 mW max

(for VDD = 5 V). If the power-up time is one dummy cycle (1.06

CS is brought high after the 10th SCLK falling edge in the

cycle and then brought low after the quiet time) and the remaining

conversion time is another cycle, i.e., 1.6

ms, then the AD7453

can be said to dissipate 7.25 mW for 2.66

ms* during each

conversion cycle.

*This figure assumes a very short time to enter power-down mode. This will

increase as the burst of clocks used to enter the power down mode is

increased.

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