•

Zero delay buffer

•

Counter reconfiguration

•

Bandwidth reconfiguration

•

Programmable output duty cycle

•

PLL cascading

•

Reference clock switchover

•

Driving of the ADC block

FPGA General Purpose I/O

The Intel MAX 10 I/O buffers support a range of programmable features.

These features increase the flexibility of I/O utilization and provide an alternative to

reduce the usage of external discrete components such as a pull-up resistor and a PCI

clamp diode.

External Memory Interface

Dual-supply Intel MAX 10 devices feature external memory interfaces solution that

uses the I/O elements on the right side of the devices together with the UniPHY IP.

With this solution, you can create external memory interfaces to 16-bit SDRAM

components with error correction coding (ECC).

Note:

The external memory interface feature is available only for dual-supply Intel MAX 10

devices.

Table 11.

External Memory Interface Performance

External Memory

Interface(3)

I/O Standard

Maximum Width

Maximum Frequency (MHz)

DDR3 SDRAM

SSTL-15

16 bit + 8 bit ECC

303

DDR3L SDRAM

SSTL-135

16 bit + 8 bit ECC

303

DDR2 SDRAM

SSTL-18

16 bit + 8 bit ECC

200

LPDDR2 SDRAM

HSUL-12

16 bit without ECC

200(4)

Related Information

External Memory Interface Spec Estimator

Provides a parametric tool that allows you to find and compare the performance of

the supported external memory interfaces in Intel FPGAs.

(3) The device hardware supports SRAM. Use your own design to interface with SRAM devices.

(4) To achieve the specified performance, constrain the memory device I/O and core power

supply variation to within ±3%. By default, the frequency is 167 MHz.

Intel® MAX® 10 FPGA Device Overview

683658 | 2021.11.01

Intel® MAX® 10 FPGA Device Overview

Send Feedback

12