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March 31, 2008

IDT80KSW0004

Datasheet

I2C Bus

This interface may be used as an alternative to the standard sRIO or JTAG ports to program the chip and to check the status of registers - including

the error reporting registers. It is fully compliant with the I2C specification, it supports master mode and slave mode, also supports both Fast-mode and

Standard-mode buses [1]. Refer to the “I2C” section for full detail.

JTAG TAP Port

This TAP interface is IEEE1149.1 (JTAG) and 1149.6 (AC Extest) compliant [10, 11]. It may also be used as an alternative to the standard sRIO or I2C

ports to program the chip and to check the status of registers - including the error reporting registers. It has 5 pins. Refer to the JTAG chapter for full

detail.

Interrupt (IRQ)

An interrupt output is provided in support of Error Management functionality. This output may be used to flag a host processor in the event of error

conditions within the device. Refer to the Error Handling chapter for full detail.

Reset

A single Reset pin is used for full reset of the CPS-12, including setting all registers to power-up defaults. Refer to the Reset & Intialization chapter for

full detail.

Clock

The single system clock (REF_CLK+ / -) is a 156.25MHz differential clock.

Rext (Rextn & Rextp)

These pins are used to establish the drive bias on the SerDes output. An external bias resistor is required. The two pins must be connected to one

another with a 12k Ohm resistor. This provides CML driver stability across process and temperature.

SPD[1:0]

Speed Select Pins. These pins define the sRIO port speed at RESET for all ports. The RESET setting may be overridden by subsequent program-

ming of the QUAD_CTRL register. SPD[1:0] = {00 = 1.25G, 01 = 2.5G, 10 = 3.125G, 11 = RESERVED}. These pins must remain STATICALLY

BIASED before power-up.