STWBC2-HP datasheet(34/96 Pages) STMICROELECTRONICS

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Figure 38. HPF (High Pass Filter) demodulator frequency response

The digital comparator compares the output of filter machine with 0. It includes hysteresis. The hysteresis

magnitude is configured through the SPI registers.

2.2.2.4

Programming

The phase modulator logic requires the following configuration sequences:

2.2.2.4.1

Enable sequence

The phase modulator enabling sequence has the following configuration steps:

Configure the P_DEMOD_CLK_L register value

Configure the P_DEMOD_CLK_H register value

Configure the P_DEMOD_HYSTERESIS register value

Program the P_DEMOD register value as follows:

Select the high pass filter frequency coefficient value bit1-0

Select the low pass filter frequency coefficient value bit3-2

Set the Enable bit7

2.2.2.4.2

Reconfigure sequence

When the phase modulator is active the reconfiguration of the filter coefficient value requires the following

operations:

Disabling the phase modulator by writing 0x00 to the P_DEMOD register

Program the P_DEMOD register with the newer value as follows:

Select the high pass filter frequency coefficient value bit1-0

Select the low pass filter frequency coefficient value bit3-2

Set the Enable bit7

2.2.2.4.3

Disable sequence

The phase demodulator disabling sequence requires to clear the P_DEMOD register value.

2.2.2.5

Operating parameters

Table 24 summarizes the IP functional target operating parameters.

STWBC2-HP

Digital AFE functions

DS13825 - Rev 1.0

page 34/96

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