LPC2364 datasheet(25/48 Pages) PHILIPS

25 / 48 page

LPC2364_66_68_1

Preliminary data sheet

Rev. 01 — 22 September 2006

25 of 48

Philips Semiconductors

LPC2364/2366/2368

Fast communication chip

With double edge controlled PWM outputs, specific match registers control the rising and

falling edge of the output. This allows both positive going PWM pulses (when the rising

edge occurs prior to the falling edge), and negative going PWM pulses (when the falling

edge occurs prior to the rising edge).

7.21.1 Features

• LPC2364/66/68 has one PWM block with Counter or Timer operation (may use the

peripheral clock or one of the capture inputs as the clock source).

• Seven match registers allow up to 6 single edge controlled or 3 double edge

controlled PWM outputs, or a mix of both types. The match registers also allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Supports single edge controlled and/or double edge controlled PWM outputs. Single

edge controlled PWM outputs all go high at the beginning of each cycle unless the

output is a constant low. Double edge controlled PWM outputs can have either edge

occur at any position within a cycle. This allows for both positive going and negative

going pulses.

• Pulse period and width can be any number of timer counts. This allows complete

flexibility in the trade-off between resolution and repetition rate. All PWM outputs will

occur at the same repetition rate.

• Double edge controlled PWM outputs can be programmed to be either positive going

or negative going pulses.

• Match register updates are synchronized with pulse outputs to prevent generation of

erroneous pulses. Software must ‘release’ new match values before they can become

effective.

• May be used as a standard timer if the PWM mode is not enabled.

• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

7.22 Watchdog timer

The purpose of the Watchdog is to reset the microcontroller within a reasonable amount of

time if it enters an erroneous state. When enabled, the Watchdog will generate a system

reset if the user program fails to ‘feed’ (or reload) the Watchdog within a predetermined

amount of time.

7.22.1 Features

• Internally resets chip if not periodically reloaded.

• Debug mode.

• Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to be

disabled.

• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

• Flag to indicate Watchdog reset.

• Programmable 32-bit timer with internal pre-scaler.

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