SN250Q datasheet(78/130 Pages) STMICROELECTRONICS

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Functional description—application modules

SN250

78/130

SC2_RATEEXP [0x4432]

SC2_SPICFG [0x442C]

0-R

SC2_RATEEXP

0-R

0-RW

SC2_RATEEXP

[3:0]

The exponential component (EXP) of the clock rate as seen in the equation:

0-R

SC_

SPIRXDRV

SC_SPIMST

SC_SPIRPT

SC_SPIORD

SC_SPIPHA

SC_SPIPOL

0-R

0-RW

SC_SPIRXDRV

[5]

Receiver-driven mode selection bit (SPI master mode only). Clearing this bit will

initiate transactions when transmit data is available. Setting this bit will initiate

transactions when the receive buffer (FIFO or DMA) has space.

SC_SPIMST

[4]

Setting this bit will put the SPI in master mode while clearing this bit will put the SPI in

slave mode.

SC_SPIRPT

[3]

This bit controls behavior on a transmit buffer underrun condition in slave mode.

Clearing this bit will send the BUSY token (0xFF) and setting this bit will repeat the

last byte. Changing this bit will only take effect when the transmit FIFO is empty and

the transmit serializer is idle.

SC_SPIORD

[2]

Clearing this bit will result in the Most Significant Bit being transmitted first while

setting this bit will result in the Least Significant Bit being transmitted first.

SC_SPIPHA

[1]

Clock phase configuration is selected with clearing this bit for sampling on the leading

(first edge) and setting this bit for sampling on second edge.

SC_SPIPOL

[0]

Clock polarity configuration is selected with clearing this bit for a rising leading edge

and setting this bit for a falling leading edge.

Rate

24 MHz

2LIN

() 2

EXP

⋅⋅

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