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Motore di ricerca datesheet componenti elettronici |
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ADN2530YCPZ-R2 Scheda tecnica(PDF) 4 Page - Analog Devices |
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ADN2530YCPZ-R2 Scheda tecnica(HTML) 4 Page - Analog Devices |
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4 / 20 page  ADN2530 Rev. A | Page 4 of 20 Parameter Min Typ Max Unit Test Conditions/Comments ALS Assert Time 2 μs Rising edge of ALS to fall of IBIAS and IMOD below 10% of nominal; see Figure 2 ALS Negate Time 10 μs Falling edge of ALS to rise of IBIAS and IMOD above 90% of nominal; see Figure 2 POWER SUPPLY VCC 3.07 3.3 3.53 V ICC7 27 32 mA VBSET = VMSET = 0 V ISUPPLY8 65 76 mA VBSET = VMSET = 0 V 1 The voltage between the pin with the specified compliance voltage and GND. 2 Specified for TA = −40°C to +85°C due to test equipment limitation. See the Typical Performance Characteristics section for data on performance for TA = −40°C to +100°C. 3 The pattern used is composed of a repetitive sequence of eight 1s followed by eight 0s at 10.7 Gbps. 4 Measured using the high speed characterization circuit shown in Figure 3. 5 The pattern used is K28.5 (00111110101100000101) at 10.7 Gbps rate. 6 The pattern used is K28.5 (00111110101100000101) at 11.3 Gbps rate. 7 Only includes current in the ADN2530 VCC pins. 8 Includes current in ADN2530 VCC pins and dc current in IMODP and IMODN pull-up inductors. See the Power Consumption section for total supply current calculation. PACKAGE THERMAL SPECIFICATIONS Table 2. Parameter Min Typ Max Unit Conditions/Comments θJ-TOP 65 72.2 79.4 °C/W Thermal resistance from junction to top of package. θJ-PAD 2.6 5.8 10.7 °C/W Thermal resistance from junction to bottom of exposed pad. IC Junction Temperature 125 °C 90% 10% ALS IBIAS AND IMOD ALS ASSERT TIME ALS NEGATE TIME t t Figure 2. ALS Timing Diagram MSET CPA ALS GND BSET IBMON IBIAS GND VCC IMODP IMODN VCC J8 J5 VEE VEE TP1 10nF ADN2530 10 μF VEE GND GND GND GND GND GND GND GND GND 50 Ω 50 Ω OSCILLOSCOPE BIAS TEE: PICOSECOND PULSE LABS MODEL 5542-219 ADAPTER: PASTERNACK PE-9436 2.92mm FEMALE-TO-FEMALE ADAPTER ATTENUATOR: PASTERNACK PE-7046 2.92mm 10dB ATTENUATOR DC-BLOCK: AGILENT BLOCKING CAPACITOR 11742A ADAPTER VBSET Z0 = 50Ω Z0 = 50Ω Z0 = 50Ω Z0 = 50Ω Z0 = 50Ω Z0 = 50Ω 750 Ω VEE VEE VMSET GND GND GND VEE VCPA TP2 10 Ω 10nF GND VEE J2 GND GND GND GND VCC VCC DATAN DATAP GND GND GND J3 GND GND BIAS TEE BIAS TEE ADAPTER ATTENUATOR ATTENUATOR DC-BLOCK DC-BLOCK Figure 3. High Speed Characterization Circuit |
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