HC705E5GRSSLASHD datasheet(39/148 Pages) NXP

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Interrupts

Custom Periodic Interrupt (CPI)

MC68HC705E5 — Rev. 1.0

General Release Specification

Interrupts

4.7 Custom Periodic Interrupt (CPI)

The CPI flag and enable bits are located in the CPI control and status

routine located at the address specified by the contents of memory

location $1FF6 and $1FF7.

The custom periodic interrupt is mask programmable to a 0.25 second,

0.5 second, or 1 second interrupt. The interrupt is generated from the

32-kHz OSC1 input by a 15-bit counter. This interrupt is under the

control of the custom periodic interrupt control and status register

located at $12.

CPIF — Custom Periodic Interrupt Flag

CPIF is a clearable, read-only status bit and is set when the 15-bit

counter changes from $7FFF to $0000. A CPU interrupt request will

be generated if CPIE is set. Clearing the CPIF is done by writing a

zero to it. Writing a one to CPIF has no effect on the bit’s value. Reset

clears CPIF.

CPIE — Custom Periodic Interrupt Enable

When this bit is cleared, the CPI interrupts are disabled. When this bit

is set, the CPU interrupt request is generated when the CPIF bit is set.

Reset clears this bit.

Address

$0012

Bit 7

654321

Bit 0

Read:

CPIF

CPIE

0000

Write:

Reset:

00000000

Figure 4-3. Custom Periodic Interrupt Control

and Status Register (CPICSR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705E5GRS/D Scheda tecnica(PDF) 39 Page - NXP Semiconductors