9DB803DFILFT datasheet(3/23 Pages) RENESAS

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ICS9DB803D

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2

IDT®

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2

ICS9DB803D

REV N 071013

Pin Descriptions for OE_INV=0

PIN #

PIN NAME

PIN TYPE

DESCRIPTION

1SRC_DIV#

Active low Input for determining SRC output frequency SRC or SRC/2.

0 = SRC/2, 1= SRC

2VDDR

PWR

3.3V power for differential input clock (receiver). This VDD should be

treated as an analog power rail and filtered appropriately.

GND

PWR

Ground pin.

SRC_IN

0.7 V Differential SRC TRUE input

SRC_IN#

0.7 V Differential SRC COMPLEMENTARY input

6OE_0

Active high input for enabling output 0.

0 =disable outputs, 1= enable outputs

7OE_3

Active high input for enabling output 3.

0 =disable outputs, 1= enable outputs

DIF_0

OUT

0.7V differential true clock output

DIF_0#

OUT

0.7V differential Complementary clock output

GND

PWR

Ground pin.

VDD

PWR

Power supply, nominal 3.3V

DIF_1

OUT

0.7V differential true clock output

DIF_1#

OUT

0.7V differential Complementary clock output

OE_1

Active high input for enabling output 1.

0 =disable outputs, 1= enable outputs

OE_2

Active high input for enabling output 2.

0 =disable outputs, 1= enable outputs

DIF_2

OUT

0.7V differential true clock output

DIF_2#

OUT

0.7V differential Complementary clock output

GND

PWR

Ground pin.

VDD

PWR

Power supply, nominal 3.3V

DIF_3

OUT

0.7V differential true clock output

DIF_3#

OUT

0.7V differential Complementary clock output

BYPASS#/PLL

Input to select Bypass(fan-out) or PLL (ZDB) mode

0 = Bypass mode, 1= PLL mode

SCLK

Clock pin of SMBus circuitry, 5V tolerant.

SDATA

I/O

Data pin for SMBus circuitry, 5V tolerant.

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