9DB803DFILFT datasheet(5/23 Pages) RENESAS

5 / 23 page

ICS9DB803D

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2

IDT®

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2

ICS9DB803D

REV N 071013

Pin Descriptions for OE_INV=1

PIN #

PIN NAME

PIN TYPE

DESCRIPTION

1SRC_DIV#

Active low Input for determining SRC output frequency SRC or SRC/2.

0 = SRC/2, 1= SRC

2VDDR

PWR

3.3V power for differential input clock (receiver). This VDD should be

treated as an analog power rail and filtered appropriately.

GND

PWR

Ground pin.

SRC_IN

0.7 V Differential SRC TRUE input

SRC_IN#

0.7 V Differential SRC COMPLEMENTARY input

6OE0#

Active low input for enabling DIF pair 0.

1 =disable outputs, 0 = enable outputs

7OE3#

Active low input for enabling DIF pair 3.

1 =disable outputs, 0 = enable outputs

DIF_0

OUT

0.7V differential true clock output

DIF_0#

OUT

0.7V differential Complementary clock output

GND

PWR

Ground pin.

VDD

PWR

Power supply, nominal 3.3V

DIF_1

OUT

0.7V differential true clock output

DIF_1#

OUT

0.7V differential Complementary clock output

OE1#

Active low input for enabling DIF pair 1.

1 =disable outputs, 0 = enable outputs

OE2#

Active low input for enabling DIF pair 2.

1 =disable outputs, 0 = enable outputs

DIF_2

OUT

0.7V differential true clock output

DIF_2#

OUT

0.7V differential Complementary clock output

GND

PWR

Ground pin.

VDD

PWR

Power supply, nominal 3.3V

DIF_3

OUT

0.7V differential true clock output

DIF_3#

OUT

0.7V differential Complementary clock output

BYPASS#/PLL

Input to select Bypass(fan-out) or PLL (ZDB) mode

0 = Bypass mode, 1= PLL mode

SCLK

Clock pin of SMBus circuitry, 5V tolerant.

SDATA

I/O

Data pin for SMBus circuitry, 5V tolerant.

9DB803DFILFT Scheda tecnica(PDF) 5 Page - Renesas Technology Corp

9DB803DFILFT Scheda tecnica(HTML) 5 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Scheda tecnica Scarica

Link URL