Rev C 1/5/15

8

2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL/ECL CLOCK

MULTIPLEXER

85356 DATA SHEET

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for

LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

The differential outputs are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must be

used for functionality. These outputs are designed to drive 50



transmission lines. Matched impedance techniques should be used

to maximize operating frequency and minimize signal distortion.

Figures 3A and 3B show two different layouts which are

recommended only as guidelines. Other suitable clock layouts may

exist and it would be recommended that the board designers

simulate to guarantee compatibility across all printed circuit and clock

component process variations.

Figure 3A. 3.3V LVPECL Output Termination

Figure 3B. 3.3V LVPECL Output Termination

R1

84



R2

84



3.3V

R3

125



R4

125



Z

o = 50

Z

o = 50

Input

3.3V

3.3V

+

_