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AD9515/PCB Scheda tecnica(PDF) 21 Page - Analog Devices

Il numero della parte AD9515/PCB
Spiegazioni elettronici  1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs
PDF  28 Pages
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD9515/PCB Scheda tecnica(HTML) 21 Page - Analog Devices

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AD9515
Rev. 0 | Page 21 of 28
Table 13. S5, S6, and S7—OUT1
S5
S6
S7
OUT1
Divide (Duty Cycle1)
OUT1
Phase
0
0
0
1
0
1/3
0
0
2 (50%)
0
2/3
0
0
3 (33%)
0
1
0
0
4 (50%)
0
0
1/3
0
5 (40%)
0
1/3
1/3
0
6 (50%)
0
2/3
1/3
0
7 (43%)
0
1
1/3
0
8 (50%)
0
0
2/3
0
9 (44%)
0
1/3
2/3
0
10 (50%)
0
2/3
2/3
0
11 (45%)
0
1
2/3
0
12 (50%)
0
0
1
0
OUT1 OFF
1/3
1
0
14 (50%)
0
2/3
1
0
15 (47%)
0
1
1
0
16 (50%)
0
0
0
1/3
17 (47%)
0
1/3
0
1/3
18 (50%)
0
2/3
0
1/3
19 (47%)
0
1
0
1/3
20 (50%)
0
0
1/3
1/3
21 (48%)
0
1/3
1/3
1/3
22 (50%)
0
2/3
1/3
1/3
23 (48%)
0
1
1/3
1/3
24 (50%)
0
0
2/3
1/3
25 (48%)
0
1/3
2/3
1/3
26 (50%)
0
2/3
2/3
1/3
27 (48%)
0
1
2/3
1/3
28 (50%)
0
0
1
1/3
29 (48%)
0
1/3
1
1/3
30 (50%)
0
2/3
1
1/3
31 (48%)
0
1
1
1/3
32 (50%)
0
0
0
2/3
2 (50%)
1
1/3
0
2/3
4 (50%)
1
2/3
0
2/3
4 (50%)
2
1
0
2/3
4 (50%)
3
0
1/3
2/3
8 (50%)
1
1/3
1/3
2/3
8 (50%)
2
2/3
1/3
2/3
8 (50%)
3
1
1/3
2/3
8 (50%)
4
0
2/3
2/3
8 (50%)
5
1/3
2/3
2/3
8 (50%)
6
2/3
2/3
2/3
8 (50%)
7
1
2/3
2/3
16 (50%)
1
0
1
2/3
16 (50%)
2
1/3
1
2/3
16 (50%)
3
2/3
1
2/3
16 (50%)
4
1
1
2/3
16 (50%)
5
0
0
1
16 (50%)
6
S5
S6
S7
OUT1
Divide (Duty Cycle1)
OUT1
Phase
1/3
0
1
16 (50%)
7
2/3
0
1
16 (50%)
8
1
0
1
16 (50%)
9
0
1/3
1
16 (50%)
10
1/3
1/3
1
16 (50%)
11
2/3
1/3
1
16 (50%)
12
1
1/3
1
16 (50%)
13
0
2/3
1
16 (50%)
14
1/3
2/3
1
16 (50%)
15
2/3
2/3
1
32 (50%)
1
1
2/3
1
32 (50%)
2
0
1
1
32 (50%)
3
1/3
1
1
32 (50%)
4
2/3
1
1
32 (50%)
5
1
1
1
Do not use
1 Duty cycle is the clock signal high time divided by the total period.
Table 14. S8—OUT0/OUT1 Phase (Delay) Select
(Used with S9 to S10)
S8
OUT0
OUT1 (Delay if S0 ≠ 0)
0
No Phase
Phase (Delay)
1/3
Phase
No Phase
2/3
No Phase
Phase (Delay) (Start High)
1
Phase (Start High)
No Phase
Table 15. S9 and S10
OUT0 or OUT1 Phase
(Depends on S8)
OUT1 Delay (S0 ≠ 0)
(Depends on S8)
S9
S10
Phase1
Fine Delay
0
0
0
0
1/3
0
1
1/16
2/3
0
2
1/8
1
0
3
3/16
0
1/3
4
1/4
1/3
1/3
5
5/16
2/3
1/3
6
3/8
1
1/3
7
7/16
0
2/3
8
1/2
1/3
2/3
9
9/16
2/3
2/3
10
5/8
1
2/3
11
11/16
0
1
12
3/4
1/3
1
13
13/16
2/3
1
14
7/8
1
1
15
15/16
1 A phase > 0 in Table 12 or overrides the phase in Table 15.



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