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HD404828RFS Scheda tecnica(PDF) 97 Page - Renesas Technology Corp |
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HD404828RFS Scheda tecnica(HTML) 97 Page - Renesas Technology Corp |
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97 / 149 page ![]() HD404829R Series 95 Bit Initial value Read/Write Bit name 3 0 W AMR3 2 0 W AMR2 0 0 W AMR0 1 — — Not used A/D mode register (AMR: $016) AMR0 0 1 Conversion time 34tcyc 67tcyc AMR3 0 0 1 1 AMR2 0 1 0 1 Analog input selection AN0 AN1 AN2 AN3 Figure 82 A/D Mode Register (AMR) A/D Data Register (ADRL: $017, ADRU: $018): Eight-bit read-only register consisting of a 4-bit lower digit and 4-bit upper digit. This register is not cleared by reset. After the completion of A/D conversion, the resultant eight-bit data is held in this register until the start of the next conversion (figures 83, 84, and 85). 3210 MSB LSB 3210 Bit 0 Bit 7 ADRU: $018 ADRL: $017 Figure 83 A/D Data Registers (ADRU, ADRL) |
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