WM8152

Production Data

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PD Rev 4.0 January 2004

18

REFERENCES

The ADC reference voltages are derived from an internal bandgap reference, and buffered to pins

VRT and VRB, where they must be decoupled to ground. Pin VRX is driven by a similar buffer, and

also requires decoupling. The output buffer from the RLCDAC also requires decoupling at pin

VRLC/VBIAS when this is configured as an output.

POWER SUPPLY

The WM8152 can run from a 5V single supply or from split 5V (core) and 3.3V (digital interface)

supplies.

POWER MANAGEMENT

Power management for the device is performed via the Control Interface. The device can be powered

on or off completely by setting the EN bit low.

All the internal registers maintain their previously programmed value in power down mode and the

Control Interface inputs remain active.

OPERATING MODES

Table 3 summarises the most commonly used modes, the clock waveforms required and the register

contents required for CDS and non-CDS operation.

MODE

DESCRIPTION

CDS

AVAILABLE

MAX

SAMPLE

RATE

TIMING

REQUIREMENTS

REGISTER

CONTENTS WITH

CDS

REGISTER

CONTENTS

WITHOUT CDS

1

Monochrome/

Colour Line-by-Line

Yes

4MSPS

MCLK max = 24MHz

MCLK:VSMP ratio is

6:1

SetReg1: 0F(hex)

SetReg1: 0D(hex)

2

Fast Monochrome/

Colour Line-by-Line

Yes

8MSPS

MCLK max = 24MHz

MCLK:VSMP ratio is

3:1

Identical to Mode

1 plus SetReg3:

bits 5:4 must be

set to 0(hex)

Identical to

Mode 1

3

Maximum speed

Monochrome/

Colour Line-by-Line

No

12MSPS

MCLK max = 24MHz

MCLK:VSMP ratio is

2:1

CDS not possible

SetReg1: 4D(hex)

4

Slow Monochrome/

Colour Line-by-Line

Yes

3MSPS

MCLK max = 24MHz

MCLK:VSMP ratio is

2n:1, n

≥ 4

Identical to

Mode 1

Identical to

Mode 1

Table 3 WM8152 Operating Modes