WM8580 datasheet(39/92 Pages) WOLFSON

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Production Data

WM8580

PD Rev 4.0 February 2007

CLOCK SELECTION

To accompany the flexible digital routing options, the WM8580 offers a clock configuration scheme

for each interface. The user can choose the interface clock from MCLK, ADCMCLK, PLLACLK or

PLLBCLK. For some interfaces, the rate can be controlled either by external LRCLK (slave mode),

internal LRCLK (master mode) or by control register. The available options are described below.

DAC INTERFACE

The DAC_CLKSEL register selects the DAC clock source from MCLK, PLLACLK or PLLBCLK. If the

digital routing has been set such that DAC1 is sourcing the S/PDIF Receiver, then PLLACLK is

automatically selected, and DACs 2/3 are powered down by default.

With RX2DAC_MODE set, DAC1 sources the S/PDIF receiver and DACs 2/3 source the PAIF (and

hence are not powered down). The PAIFRX_LRCLK determines the sampling rate, so the S/PDIF

sampling rate must be synchronised with PAIF_LRCLK. Also, use of the S/PDIF receiver means that

PLLACLK and PLLBCLK are not available, and the MCLK applied to the DACs must be at a standard

audio rate.

The rate at which the DACs operate is determined by the DAC Rate module, divided down from the

MCLK signal. It calculates the rate based on the digital routing setup, and selects between

128/192/256/384/512/768/1152fs. When sourcing from the PAIF Receiver, PAIFRX_LRCLK (internal

or external) is used in the rate calculation. When sourcing from the SAIF Receiver, SAIF_LRCLK

(internal or external) is used in the rate calculation. When DAC1 is sourcing directly from the S/PDIF

receiver, the sub-fram clock, SFRM_CLK, is used in the rate calculation. However this can be

changed by setting the RX2DAC_MODE register bit, allowing the PAIF_LRCLK to determine the

sampling rate.

Figure 26 DAC Clock Selection

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

CLKSEL

08h

1:0

DAC_CLKSEL

DAC clock source

00 = MCLK pin

01 = PLLACLK

10 = PLLBCLK

11 = MCLK pin

R15

DAC

CONTROL 1

0Fh

RX2DAC_MODE

DAC oversampling rate and power down

control (only valid when DAC_SRC = 00,

DAC1 data sourced from S/PDIF receiver)

0 = SFRM_CLK determines

oversampling rate, DACs 2/3 powered

down

1 = PAIFRX_LRCLK determines

oversampling rate, DACs 2/3 source

PAIF Receiver

Table 33 DAC Clock Control

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