WM8580 datasheet(73/92 Pages) WOLFSON

73 / 92 page

Production Data

WM8580

PD Rev 4.0 February 2007

R40

GPO3

GPO6OP[3:0]

GPO5OP[3:0]

001010100

R41

GPO4

GPO8OP[3:0]

GPO70P[3:0]

001110110

R42

GPO5

GPO10OP[3:0]

GPO9OP[3:0]

010011000

R43

INTSTAT

Error Flag Interupt Status Register

R44

SPDRXCHAN 1

Channel Status Register 1

R45

SPDRXCHAN 2

Channel Status Register 2

R46

SPDRXCHAN 3

Channel Status Register 3

R47

SPDRXCHAN 4

Channel Status Register 4

R48

SPDRXCHAN 5

Channel Status Register 5

R49

SPDSTAT

S/PDIF Status Register

R50

PWRDN 1

ALLDACPD

DACPD[2:0]

ADCPD

PWDN

001111110

R51

PWRDN 2

SPDIFRXD SPDIFTXD SPDIFPD

PLLBPD

PLLAPD

OSCPD

000111110

R52

READBACK

READEN

CONTREAD

READMUX[2:0]

000000000

R53

RESET

n/a

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

PLLA 1/

DEVID1

00h

8:0

PLLA_K[8:0]

100100001

PLLA 2/

DEVID2

01h

8:0

PLLA_K[17:9]

101111110

3:0

PLLA_K[21:18]

1101

Fractional (K) part of PLLA frequency ratio (R).

Value K is one 22-digit binary number spread over registers R0,

R1 and R2 as shown.

Reading from these registers will return the device ID.

R0 returns 10000101 = 80h

R1 returns 10000000 = 85h

Device ID readback is not possible in continuous readback mode

(CONTREAD=1).

PLLA 3/

DEVREV

02h

7:4

PLLA_N[3:0]

0111

Integer (N) part of PLLA frequency ratio (R).

Use values in the range 5 ≤ PLLA_N ≤ 13 as close as possible to

Reading from this register will return the device revision number.

PRESCALE_A

PLL Pre-scale Divider Select

0 = Divide by 1 (PLL input clock = oscillator clock)

1 = Divide by 2 (PLL input clock = oscillator clock

÷ 2)

Note: PRESCALE_A must be set to the same value as

PRESCALE_B in PLL S/PDIF receiver mode.

POSTSCALE_A

PLL Post-scale Divider Select

PLL S/PDIF Receiver Mode

POSTSCALE_A is used to configure a 256fs or 128fs PLLACLK,

POSTSCALE_B is not used. Refer to Table 44.

PLL User Mode

Used in conjunction with the FREQMODE_x bits. Refer to Table

43.

PLLA 4

03h

4:3

FREQMODE_A[

1:0]

PLL Output Divider Select

PLL S/PDIF Receiver Mode

FREQMODE_A is automatically controlled. FREQMODE_B is not

used.

PLL User Mode

Used in conjunction with the POSTSCALE_x bits. Refer to Table

43.

PLLB 1

04h

8:0

PLLB_K[8:0]

100100001

Fractional (K) part of PLLB frequency ratio (R).

Value K is one 22-digit binary number spread over registers R4,

R5 and R6 as shown.

WM8580 Scheda tecnica(PDF) 73 Page - Wolfson Microelectronics plc

WM8580 Scheda tecnica(HTML) 73 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

Scheda tecnica Scarica

Link URL