MC12009 MC12011 MC12013

6

MOTOROLA RF/IF DEVICE DATA

Pi

Test Limits

Pin

Under

–30

°C

+25

°C

+85

°C

Characteristic

Symbol

Under

Test

Min

Max

Min

Max

Min

Max

Unit

Power Supply Drain Current

ICC1

8

–88

–80

–80

mAdc

pp y

ICC2

6

5.2

5.2

5.2

mAdc

Input Current

IinH1

15

11

12

13

375

375

375

375

250

250

250

250

250

250

250

250

µAdc

IinH2

4

5

1.7

1.7

6.0

6.0

2.0

2.0

6.0

6.0

2.0

2.0

6.4

6.4

mAdc

IinH3

5

0.7

3.0

1.0

3.0

1.0

3.6

IinH4

9

10

100

100

100

100

100

100

µAdc

Leakage Current

IinL1

15

11

12

13

–10

–10

–10

–10

–10

–10

–10

–10

–10

–10

–10

–10

µAdc

IinL2

9

10

–1.6

–1.6

–1.6

–1.6

–1.6

–1.6

mAdc

Reference Voltage

VBB

14

3.67

3.87

Vdc

Logic ‘1’ Output Voltage

VOH1

(Note 4.)

2

3

3.900

3.900

4.110

4.110

4.000

4.000

4.190

4.190

4.070

4.070

4.300

4.300

Vdc

VOH2

7

2.4

2.6

2.8

Logic ‘0’ Output Voltage

VOL1

(Note 4.)

2

3

3.070

3.070

3.385

3.385

3.110

3.110

3.410

3.410

3.135

3.135

3.445

3.445

Vdc

VOL2

7

0.94

0.80

0.72

Logic ‘1’ Threshold Voltage

VOHA

(Note 5.)

2

3

3.880

3.880

3.980

3.980

4.050

4.050

Vdc

Logic ‘0’ Threshold Voltage

VOLA

(Note 6.)

2

3

3.405

3.405

3.430

3.430

3.465

3.465

Vdc

Short Circuit Current

IOS

7

–65

–20

–65

–20

–65

–20

mAdc

4. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and

ground voltages must be maintained between tests. The clock input is the waveform shown.

5. In addition to meeting the output levels specified, the device must divide by 5, 8 or 10 during this test. The clock

input is the waveform shown.

6. In addition to meeting the output levels specified, the device must divide by 6, 9 or 11 during this test. The clock

input is the waveform shown.

Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been

established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.

Outputs are terminated through a 50

Ω resistor to –2.0 V. Test procedures are shown for only one gate. The other gates are tested in the same

manner.

VIHmax

VILmin

Clock Input