RT600 datasheet(4/171 Pages) NXP

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RT600

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Product data sheet

Rev. 2.2 — 25 January 2024

4 of 173

NXP Semiconductors

RT600

Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4

Audio DSP CPUs

operated when the chip is in reduced power mode, using either the 32 kHz clock or

an externally supplied clock.The USART also provides partial support for LIN2.2.

- An I2C-bus interface with multiple address recognition, and a monitor mode. It

supports 400 Kb/sec Fast-mode and 1 Mb/sec Fast-mode Plus. It also supports

3.4 Mb/sec high-speed when operating in slave mode.

- An SPI interface.

- An I2S (Inter-IC Sound) interface for digital audio input or output. Each I2S

supports up to four channel-pairs.



One high-speed SPI interface (Flexcomm Interface 14 only) supporting 50 MHz

operation.



One additional I2C interface available on some device configurations (see specific

device data sheet for more information). This interface is intended primarily for

communication with an external power management device (PMIC), but can be

used for other purposes when the application does not use an external PMIC.



One I3C bus interface.



A digital microphone interface supporting up to 8 channels with associated

decimators and Voice Activation Detect. One pair of channels can be streamed

directly to I2S. The DMIC supports DMA.



One 32-bit SCTimer/PWM module (SCT). Multi-purpose timer with extensive

event-generation, match/compare, and complex PWM and output control features.

- Supports DMA and can trigger external DMA events.

- Supports fractional match values for high resolution.

- State machine capability.

- 8 general-purpose inputs.

- 10 general-purpose/PWM outputs

- 16 matches or captures

- 16 events

- 32 states



Five general purpose, 32-bit timer/counter modules with PWM capability.

- Each timer supports four match outputs and four capture inputs.

- Match register auto-reload from shadow registers.

- It supports DMA and can trigger external DMA events.



24-bit multi-rate timer module with four channels, each capable of generating

repetitive interrupts at different programmable frequencies.



Two Windowed Watchdog Timers (WDT) with dedicated watchdog oscillator.



Frequency measurement module to determine the frequency of a selection of

on-chip or off-chip clock sources.



Real-Time Clock (RTC) with independent power supply and dedicated oscillator.

Integrated wake-up timer can be used to wake the device up from low-power

modes. The RTC includes eight 32-bit general purpose registers which can retain

content when power is removed from the rest of the chip.



Ultra-low power micro-tick timer running from the watchdog oscillator with capture

capability for timestamping. Can be used to wake the device up from low-power

modes.



64-bit OS Event Timer common to the Cortex-M33 and DSP processors with

individual match/capture and interrupt generation logic.



CRC engine block can calculate a CRC on supplied data using one of three

standard polynomials. The CRC engine supports DMA.

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